Operation mode setting apparatus on a single chip microprocessor

Claim 1

An operation mode setting apparatus on a single chip microprocessor having an internal bus which comprises: an n-bit operation mode-setting register means for storing the data which specifies one of 2 n operation modes, which modes include two start operation modes; a single external pin connection for receiving externally supplied logic level signals for specifying one of the two start operations modes; a first circuit means for generating, according to the logic level signal on said external connection pin, the data for designating the start operation mode; a second circuit means for causing mode-setting data generated through a user program execution to select one of the 2 n operation modes; a selector means for allowing said data for designating the start operation mode to be latched into the operation mode-setting register means at the reset state of the microprocessor and for selectively allowing said mode-setting data on the internal bus of the microprocessor to be latched into the operation mode-setting means after the reset state of the microprocessor; and means for preventing data from being written in the mode-setting register means, until the microprocessor is again brought to a reset state after data is written in the mode-setting register means through said user program execution after the release of the reset state of the microprocessor.