Cancellation of scatter jamming

Claim 2

A signal processor for receiving desired signals and undesired signals and for cancelling the undesired signals comprising: a main signal transmitting channel capable of imparting high gain to desired signals and relatively low gain to most undesired signals, a subtracting circuit connected in said main signal transmitting channel between its input and output; two auxiliary signal transmitting channels capable of imparting low gain to said desired signals and to said undesired signals, a delay line connected in series with one of said auxiliary channels to provide a delay to desired and undesired signals in said channel such as to bring said undesired signals into time synchronization with undesired signals in said main signal transmitting channel, means including a separate correlator connected between the output of said main channel and each of said auxiliary channels to correlate said desired and undesired signals and to generate error signals adjusted in phase and in amplitude to correspond to the undesired signals in said main channel, and means for applying said error signals to said subtracting circuit to reduce the magnitude of said undesired signals at the output of said main channel.

Claim 3

A signal processor substantially as claimed in claim 1 in which said main signal transmitting channel includes a directional antenna to impart said high gain to desired signals received in its main lobe.

Claim 4

A signal processor substantially as claimed in claim 1 in which said auxiliary signal transmitting channels include an omni-directional antenna for receiving radiant energy from all directions and for imparting essentially equal gain to desired and undesired signals.

Claim 5

A signal processor for eliminating undesired signals from among desired signals where the undesired signals include first and second signal group differing from each other primarily in their time occurrence with the second group being delayed in time with respect to the first, said processor comprising: a main signal transmission channel including an input to which is applied said desired signals and said first and second groups of undesired signals, and including an output for signals as transmitted therethrough; first and second auxiliary signal transmission channels each including an input to which is applied at least said first group of undesired signals and each including an output, said second auxiliary channel further including means for delaying signals transmitted therethrough for a time corresponding to said time delay between said first and second undesired signal groups so as to provide, at the output of this channel, signals corresponding in time to said second undesired signal group; first correlation means connected to receive output signals from said main and first auxiliary channels and operative to produce a first correcting signal by correlation of received signals of said first undesired group; second correlation means connected to receive output signals from said main and second auxiliary channels and operative to produce a second correcting signal by correlation of received signals of said second undesired group and of signals of said first group placed in time correspondence with said second group by said time delay means; and signal subtracting means connected in said main channel to receive said first and second correcting signals and operative to subtract them from the signals as transmitted by said main channel so as to at least partially cancel both said groups of undesired signals while passing said desired signals.

Claim 6

A signal processor for eliminating undesired signals from among desired signals where the undesired signals include first and second signal group differing from each other primarily in their time occurrence with the second group being delayed in time with respect to the first, said processor comprising: a main signal transmission channel including an input to which is applied said desired signals and said first and second groups of undesired signals, and including an output for signals as transmitted therethrough; first and second auxiliary signal transmission channels each including an input to which is applied at least said first group of undesired signals and each including an output, said second auxiliary channel further including means for delaying signals transmitted therethrough for a time corresponding to said time delay between said first and second undesired signal groups so as to provide, at the output of this channel, signals corresponding in time to said second undesired signal group; first correlation means connected to receive output signals from said main and first auxiliary channels and operative to produce a first correcting signal by correlation of received signals of said first undesired group; second correlation means connected to receive output signals from said main and second auxiliary channels and operative to produce a second correcting signal by correlation of received signals of said second undesired group and of signals of said first group placed in time correspondence with said second group by said time delay means; and signal subtracting means connected in said main channel to receive said first and second correcting signals and operative to subtract them from the signals as transmitted by said main channel so as to at least partially cancel both said groups of undesired signals while passing said desired signals.

Claim 7

A processor as defined in claim 4 wherein said second group of undesired signals includes a plurality of signals each differently delayed in time with respect to said first undesired signal group, wherein said time delay means comprises a plurality of delay elements each providing a delay period corresponding to the time delay of one undesired signal of said second group, and wherein said second correlation means comprises a plurality of correlators each connected to one of said time delay elements, whereby said second correcting signal as received by said subtracting means may provide at least partial cancellation of a plurality of undesired signals of said second group having different time delays.

Claim 8

A signal processor for cancelling a plurality of undesired signals differing primarily in their time occurrence, comprising: a first processor channel connected to receive said undesired signals; a second processor channel connected to receive said undesired signals at a plurality of distinct times each differently delayed with respect to the time of reception in said first channel; a plurality of signal correlators each operative to produce a correcting signal by correlation of applied signals; means coupling the output of said second channel to said correlators to provide one applied signal to each said correlator; means coupling the output of said first channel to each of said correlators with a time delay for each differing correspondingly to said differences in signal reception times in said second channel, to provide another applied signal to each of said correlators enabling each to produce a correcting signal by correlation of second channel signals with first channel signals as thus delayed; and a subtracting circuit in said second channel connected to receive the correcting signals produced by said correlators and operative to subtract said correcting signals from the signal content of said second channel to provide at least partial cancellation of undesired signals therein.

Claim 9

A signal processor for cancelling a plurality of undesired signals differing primarily in their time occurrence, comprising: a first processor channel connected to receive said undesired signals; a second processor channel connected to receive said undesired signals at a plurality of distinct times each differently delayed with respect to the time of reception in said first channel; a plurality of signal correlators each operative to produce a correcting signal by correlation of applied signals; means coupling the output of said second channel to said correlators to provide one applied signal to each said correlator; means coupling the output of said first channel to each of said correlators with a time delay for each differing correspondingly to said differences in signal reception times in said second channel, to provide another applied signal to each of said correlators enabling each to produce a correcting signal by correlation of second channel signals with first channel signals as thus delayed; and a subtracting circuit in said second channel connected to receive the correcting signals produced by said correlators and operative to subtract said correcting signals from the signal content of said second channel to provide at least partial cancellation of undesired signals therein.