Vertical MOS-FET devices having a planar multicell structure

Claim 1

A vertical MOS-FET semiconductor device having a planar multicell structure, which comprises: a semiconductor body; a layer of a first conductivity type at the surface of said body which comprises the drain zone of said MOS-FET device; a plurality of identical elementary cells, each in triangular form, each cell comprising a first highly-doped island of the second conductivity type in said layer which defines the form of said cell and a second highly-doped island of the first conductivity type in said first island, said second island being in the shape of a loop and having said triangular form, and said second island comprising the source zone of said MOS FET device; a shortcircuit region in the center of the loop of said second island adjacent the surface of said device, at which region said first and second islands are connected together; a channel zone formed adjacent said surface between the outer perimeter of said second island and the perimeter of said first island; a gate region extending over said channel region; and means for optimizing the overall length of said channel zone per unit of surface area (filling factor), which comprises a plurality of identical complementary cell elements, each having a construction similar to that of said elementary cells and having an hexagonal form, said complementary cell elements being located between adjoining apices of adjacent elementary cells.