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US4626825A Expired / Lapsed US ⏱️ 0.0 years remaining

Logarithmic conversion apparatus

Assignee: Philips Semiconductors Inc
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Filing: 1985-07-02
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Granted: 1986-12-02
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Expires: 2005-07-02
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Abstract

Abstract A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number. A decoder receives the exponential component of the logarithmic representation and a Point Set Output value, a scale value for said integer, and supplies a shifted signal. The shifted signal is supplied to a shifter along with the first number and the shifter shifts the first number by the shift signal to produce the integer.

Inventors

  • 👤 Wayne P. Burleson
  • 👤 Lawrence F. Wagner
  • 👤 Korbin S. Van Dyke

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 21:29
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/14; H03M7/24; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0307; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/4833

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 251 words
A digital apparatus for converting a digital binary integer having a plurality of bits into logarithmic representation comprising: means for determining the bit position of the leading non-zero bit of said integer; means for shifting said integer such that the leading non-zero bit is the left most bit; table means for receiving said shifted integer and for providing a number representative of the mantissa portion of the logarithm of said shifted number, said table means having a plurality of interconnected comparators, arranged in an array and for storing a plurality of digital values in a monotonically increasing or decreasing order; each comparator having means for receiving said shifted integer, means for comparing said shifted integer to the digital value stored in said comparator, means for generating a comparison signal in response to said comparison; means for receiving the comparison signal from an immediately adjacent comparator, means responsive to the comparison signal from each comparator and the comparison signal from the adjacent comparator for generating an output signal; means for receiving the plurality of output signals and for generating said number representative of the mantissa portion of the logarithm of said shifted number; and encoding means for receiving a point-set input value and the number of binary positions shifted by said shifting means and for generating the exponent portion of the logarithm of said integer, wherein said point-set input value is the scale value for said integer, whereby said mantissa portion and said exponent portion from the logarithmic representation of said integer.
Claim 2
Dependent Claim 251 words
A digital apparatus for converting a digital binary integer having a plurality of bits into logarithmic representation comprising: means for determining the bit position of the leading non-zero bit of said integer; means for shifting said integer such that the leading non-zero bit is the left most bit; table means for receiving said shifted integer and for providing a number representative of the mantissa portion of the logarithm of said shifted number, said table means having a plurality of interconnected comparators, arranged in an array and for storing a plurality of digital values in a monotonically increasing or decreasing order; each comparator having means for receiving said shifted integer, means for comparing said shifted integer to the digital value stored in said comparator, means for generating a comparison signal in response to said comparison; means for receiving the comparison signal from an immediately adjacent comparator, means responsive to the comparison signal from each comparator and the comparison signal from the adjacent comparator for generating an output signal; means for receiving the plurality of output signals and for generating said number representative of the mantissa portion of the logarithm of said shifted number; and encoding means for receiving a point-set input value and the number of binary positions shifted by said shifting means and for generating the exponent portion of the logarithm of said integer, wherein said point-set input value is the scale value for said integer, whereby said mantissa portion and said exponent portion from the logarithmic representation of said integer.

References Cited (Backward Citations)

US4078250A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-12-01 1990-06-02 1990-12-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-12-01 1994-06-02 1994-12-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-12-01 1998-06-02 1998-12-02 $7700.00 Window Closed / Lapsed

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