Patent US6350231B1 successfully refreshed from Google Patents.
Patent US4626798A successfully refreshed from Google Patents.
US4626798A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-lock loop including integrated circuit voltage controlled oscillator
Assignee: Verizon Laboratories Inc
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Filing: 1985-12-11
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Granted: 1986-12-02
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Expires: 2005-12-11
Abstract
Abstract A voltage controlled oscillator (VCO) is described which comprises a plurality of inverter stages of odd number connected in a ring with the output of each stage connected to the input of the next stage via a voltage controlled impedance provided by the transconductance of pass transistors. In one embodiment, this VCO is incorporated into a Phase-Lock Loop circuit, in which the gates of the pass transistors are connected to a control circuit which provides a variable biasing voltage to the gates inresponse to speed-up or slow-down signals provided by a phase detector. The bias on the gates adjusts the frequency of the voltage controlled oscillator, in accordance with the speed-up or slow-down signal. The phase detector is coupled to a stream of input data pulses and to a reference train of clock pulses provided by the voltage controlled oscillator. The phase detector determines whether the frequency of the clock pulses are faster or slower than the frequency of the data pulses and produces either a speed-up signal or a slow-down signal, depending upon the relative speed. These slow-down and speed-up signals are fed to control means responsive to the signals to increase or decrease the bias voltage applied to the gates of the pass transistors.
Inventors
- 👤 Jeffrey A. Fried
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:28
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
39 words
A voltage controlled oscillator comprising an odd number of inverter stages connected in a ring for producing an oscillating voltage; the output of each stage being connected to the input of the next stage via a voltage controllable impedance.
Claim 2
Dependent Claim
39 words
A voltage controlled oscillator comprising an odd number of inverter stages connected in a ring for producing an oscillating voltage; the output of each stage being connected to the input of the next stage via a voltage controllable impedance.
Claim 3
Dependent Claim
18 words
The voltage controlled oscillator of claim 1 wherein the voltage controllable impedance is the transconductance of a transistor.
Claim 4
Dependent Claim
53 words
The voltage controlled oscillator of claim 2 wherein each of the inverter stages comprises a pair of MOS devices; each having source, drain and gate electrodes, the source and drain electrodes of which are connected in series between a positive power supply and ground and the gate electrodes of which are coupled together.
Claim 5
Dependent Claim
118 words
A voltage controlled oscillator comprising N number of transistor inverter stages, each having input and output terminals and an inverter, and a pass transistor coupled in series between stages, connected in a ring for producing a series of voltage output pulses of predetermined frequency; such frequency being established by a bias voltage applied to the pass transistors, said pass transistors having a gate electrode, said pass transistors controlling the time delay of the inverter stages, and wherein the gate electrode of the pass transistors is adapted to be coupled to a source of variable voltage for providing said bias voltage to vary the transconductance of the pass transistors and thereby vary the time delay of the inverter stages.
Claim 6
Dependent Claim
118 words
A voltage controlled oscillator comprising N number of transistor inverter stages, each having input and output terminals and an inverter, and a pass transistor coupled in series between stages, connected in a ring for producing a series of voltage output pulses of predetermined frequency; such frequency being established by a bias voltage applied to the pass transistors, said pass transistors having a gate electrode, said pass transistors controlling the time delay of the inverter stages, and wherein the gate electrode of the pass transistors is adapted to be coupled to a source of variable voltage for providing said bias voltage to vary the transconductance of the pass transistors and thereby vary the time delay of the inverter stages.
Claim 7
Dependent Claim
93 words
The oscillator of claim 4 in which the inverter comprises a pair of MOS transistors having gate, drain and source electrodes, one of which transistors is a p-channel device and the other of which is an n-channel device and wherein the drain and gate electrodes of each are coupled in series between a positive D.C. voltage supply and ground and with the gate electrodes of each coupled together and to the input terminal of the inverter stage and the drain electrodes being coupled together and to the output terminal of the inverter stage.
Claim 8
Dependent Claim
22 words
The oscillator of claim 5 in which said pass transistors have drain and source electrodes coupled in series with said inverter stages.
Claim 9
Dependent Claim
27 words
The oscillator of claim 5 wherein the pass transistors are coupled to the input or output terminal of the inverter stages and through a capacitor to ground.
Claim 10
Dependent Claim
179 words
A digital Phase-Lock Loop circuit for providing a reference train of clock pulses synchronized with an incoming stream of data pulses comprising: (a) a voltage controlled oscillator, having a plurality of inverter stages of odd number connected in a ring with the output of each stage connected to the input of the next stage, and a voltage controlled impedance coupled to said inverter stages and connected to a variable voltage source, for providing said reference train of clock pulses, the frequency of which is controlled by the voltage controlled impedance; (b) a phase detector adapted to be coupled to said stream of data pulses and to said reference train of clock pulses for determining whether the frequency of the clock pulses is faster or slower than the frequency of the data pulses and for producing a speed-up signal if the clock pulses are slower or a slow-down signal if the clock pulses are faster; and (c) control means responsive to the speed-up or slow-down signals for increasing or decreasing the voltage from said variable voltage source in response thereto.
Claim 11
Dependent Claim
179 words
A digital Phase-Lock Loop circuit for providing a reference train of clock pulses synchronized with an incoming stream of data pulses comprising: (a) a voltage controlled oscillator, having a plurality of inverter stages of odd number connected in a ring with the output of each stage connected to the input of the next stage, and a voltage controlled impedance coupled to said inverter stages and connected to a variable voltage source, for providing said reference train of clock pulses, the frequency of which is controlled by the voltage controlled impedance; (b) a phase detector adapted to be coupled to said stream of data pulses and to said reference train of clock pulses for determining whether the frequency of the clock pulses is faster or slower than the frequency of the data pulses and for producing a speed-up signal if the clock pulses are slower or a slow-down signal if the clock pulses are faster; and (c) control means responsive to the speed-up or slow-down signals for increasing or decreasing the voltage from said variable voltage source in response thereto.
Claim 12
Dependent Claim
208 words
The Phase-Lock Loop circuit of claim 8 wherein the phase detector comprises an Exclusive OR GATE having its input terminals coupled to said reference train of clock pulses and to said incoming stream of data pulses and its output terminal coupled to first and second AND GATES, the other terminal of said AND GATE being coupled to the incoming stream of data pulses and the other terminal of the second AND GATE being coupled to said reference train of clock pulses; and an enable signal formed by coupling the reference train of clock pulses and the incoming stream of data pulses through a NOR GATE and slightly time-delaying the output of said NOR GATE, said enable signal being provided to said first and second AND GATES, whereby an output speed-up signal, comprising a train of pulses, is provided from said first AND GATE in the event the reference train of clock pulses is of lower frequency than the input incoming stream of data pulses and wherein a slow-down signal comprising a train of pulses is provided from the second AND GATE in the event the reference train of clock pulses is operating at a frequency which is greater than the frequency of the incoming stream of data pulses.
Claim 13
Dependent Claim
56 words
A Phase-Lock Loop circuit of claim 8 in which the control means comprises a capacitive network coupled between the phase detector and ground and the voltage controlled impedance of the voltage controlled oscillator and, further including a transistor switch which lowers the bias voltage applied to the variable controlled impedance in response to a slow-down signal.
Claim 14
Dependent Claim
52 words
A Phase-Lock Loop circuit of claim 8 in which the voltage controlled impedance comprises pass transistors having a gate electrode and the control means comprises a low-pass filter formed of a capacitve network coupled between the phase detector and ground which controls the bias voltage to the gates of the pass transistors.
References Cited (Backward Citations)
US3428913A
Cited
US4072910A
Cited
US4105950A
Cited
US4079338A
Cited
US4458165A
Cited
US4517532A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |