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Double heterostructure light-emitting semiconductor device

Assignee: Toshiba Corp
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Filing: 1985-02-14
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Granted: 1986-11-25
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Expires: 2005-02-14
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Abstract

Abstract A double heterostructure light-emitting semi-conductor device includes a p-GaAs substrate having a first electrode formed on one surface and a current confining layer on the other surface; a confined current conduction layer; and a light-emitting layer structure formed on the current confining layer and the confined current conduction layer. A capping layer of GaAs having a second electrode is formed on the light-emitting layer structure. A light exit window layer for exiting the emitted light is constructed by a thin film of the capping layer.

Inventors

  • 👤 Tadashi Komatsubara
  • 👤 Tetsuo Sadamasa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 04:35
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/81; H10H20/816; H10H20/8162

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 161 words
A double heterostructure light-emitting semiconductor device comprising: a semiconductor substrate selected from a first conductivity type GaAs substrate and a first conductivity type GaAlAs substrate; a first electrode provided on one surface of said semiconductor substrate; a current confining layer formed on the other surface of said semiconductor substrate; a confined current conduction layer formed in a selected region of said current confining layer; a light-emitting semiconductor layer structure having a double heterojunction and formed on said current confining layer including said selected region; and a capping layer formed of a second conductivity type GaAs layer on the free surface of said light-emitting semiconductor layer structure; wherein said capping layer has a carrier concentration of 1×10 18 /cm 3 or higher and includes first and second portions, said first portion being used as a light exit window layer and the thickness thereof being in a range of 0.2 to 2.0 microns and said second portion having a second electrode provided thereon.
Claim 2
Dependent Claim 161 words
A double heterostructure light-emitting semiconductor device comprising: a semiconductor substrate selected from a first conductivity type GaAs substrate and a first conductivity type GaAlAs substrate; a first electrode provided on one surface of said semiconductor substrate; a current confining layer formed on the other surface of said semiconductor substrate; a confined current conduction layer formed in a selected region of said current confining layer; a light-emitting semiconductor layer structure having a double heterojunction and formed on said current confining layer including said selected region; and a capping layer formed of a second conductivity type GaAs layer on the free surface of said light-emitting semiconductor layer structure; wherein said capping layer has a carrier concentration of 1×10 18 /cm 3 or higher and includes first and second portions, said first portion being used as a light exit window layer and the thickness thereof being in a range of 0.2 to 2.0 microns and said second portion having a second electrode provided thereon.
Claim 3
Dependent Claim 80 words
A double heterostructure light-emitting semiconductor device according to claim 1, wherein said current confining layer is a layer selected from said second conductivity type GaAs layer and a second conductivity type GaAlAs layer; said light-emitting layer structure includes a first conductivity type GaAlAs clad layer, an active layer selected from a first conductivity type GaAlAs layer and a first conductivity type GaAs layer, and a second conductivity type GaAlAs clad layer, which are sequentially superposed on said current confining layer.
Claim 4
Dependent Claim 24 words
A double heterostructure light-emitting semiconductor device according to claim 2, wherein said confined current conduction layer is formed of said first conductivity type GaAs.

References Cited (Backward Citations)

US4010483A Cited
US4212021A Cited
GB2033155A Cited
JPS5880882A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-11-24 1990-05-26 1990-11-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-11-24 1994-05-26 1994-11-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-11-24 1998-05-26 1998-11-25 $7700.00 Window Closed / Lapsed

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