Compression/decompression system for transmitting and receiving compressed picture information arranged in rows and columns of pixels

Claim 2

In a system for line-wise compressing and decompressing a picture field which is made of a plurality of rows and columns of pixel data, a compression device comprising: a first input for receiving said picture field pixel data; a read/write memory organized on a word basis connected to store at least a line of said pixel data received from said first input; a first shift register coupled to receive a row of said pixel data from said first input; a second shift register connected to receive pixel data from said read/write memory which, during a memory cycle with said first register, receives the preceding row of pixel data having the same column position as said first register data; a compression translator connected to said first and second shift registers, said compression translator generating from line pixels received from said first and second shift registers a series of compression bits, successive lines of pixel data generating successive groups of compression bits which have neither fill bits nor end of line bits; and, a series to parallel converting buffer fed through a first input by said compression translator, and buffer having a dynamic second input and output for communicating with a parallel local communication bus.

Claim 3

A system as claimed in claim 1, further comprising a decompression device which comprises a third input for receiving the compression bits, a second, word-wise organized read/write memory for accommodating at least the binary pixel data of a complete picture line, a third shift register with a parallel input and a parallel output for storing, during a second memory operation, a third series of data bits of a directly preceding picture line from the second read/write memory addressed by a third address, and for presenting said third series, by way of second shift control of the third shift register, to a decompression translator, a third output of the decompression translator connected to the series input of a fourth shift register to present thereto a series of data bits of a current picture line, and to present said series of data bits to the decompression translator on an output of the fourth shift register, said fourth shift register also comprising a parallel output for writing, during said second memory operation, a fourth series of data bits of the current picture line back into the second read/write memory, said second read/write memory addressed by a fourth address which occupies a fixed relative position with respect to the third address, a code word recognizer which comprises a parallel/series converting input element and an end-around coupled sequencer for signalling the recognition of a code word to the decompression translator; a second sequential logic element which comprises at least two states in order to activate said parallel/series converting input element in a third state until a code word has been recognized and to activate said second shift control in a fourth state in reaction thereto until a series of data bits in agreement with the group of significant compression bits of the code word thus recognized has been presented to said fourth shift register.

Claim 4

A decompression device as claimed in claim 2, wherein a counting element is provided for counting the data bits presented to said fourth shift register after the recognition of a horizontal code, and a comparison element for comparing the counting sum with a counting sum of a "make-up" or a "terminate" code word which is translated by the code word recognizer from a horizontal code word upon recognition thereof.

Claim 5

A decompression device as claimed in claim 3, wherein said fourth shift register has a first-in-first-out organization, the parallel output thereof being connected to a second communication bus together with the second read/write memory.

Claim 6

A system as claimed in claim 1 wherein each successive group of compression data indicates a transistion between a black pixel and an adjacent white pixel in a line of pixel data.

Claim 7

A system as claimed in claim 5, wherein during the processing of the first line of the picture field a one-colour fiduciary zeroth line is presented to the compression translator.

Claim 8

A compression device for use in a system as claimed in claim 5 wherein said memory cycle is a read-before-write operation under direct-memory access (DMA) control.

Claim 9

A scanning device for a document, comprising a compression device as claimed in claim 7, further comprising a picture buffer which is fed by a scanning element in order to accommodate all data of a picture field before further processing.

Claim 10

A compression device as claimed in claim 5, wherein there is provided a sequential logic element which has at least two states in order to activate the shift control (ISE) of said first and second shift register in a first state until a group of significant compression bits has been formed, to deactivate in reacation thereto said shift control in a second state, to activate said first output (IES) until said group of significant compression bits has been presented compltely on said first output, and to return in reaction thereto to said first state.

Claim 11

A compression device as claimed in claim 9, wherein said second state has a substate in order to enable, together with the presentation of a last code bit of group of significant compression bits, the shift control of the next data bit.

Claim 12

A compression device as claimed in claim 9, wherein said compression translator comprises programmable logic array means for receiving the information of at least two pixels (x, x-1) of the actual line, of at least two pixels in corresponding positions on the directly preceding line (y, y-1), and of at least three further adjacent pixels (BY-2, BY-3, BY-4) on the same directly preceding line, said programmable logic array means having first generating means for generating transistion-dependent pixel line status signals (LSTO:3), second generating means for receiving said pixel line status signals, and being coupled by a hold element for constituting an end around sequencer and generating horizontal code status signals, and code word rest length signals (C.0.DLO:3) which are generated by a counter to generate the group of compression code bits as output signals.

Claim 13

A compression device as claimed in claim 11, wherein said counter is a code word rest length counter, fed by a two-input-one-output multiplexer, said multiplexer being fed by code word rest length signals (HC.0.DLO:3) from said counter and by the line status signals (LSTO:2), the code word rest length counter having at least one position for therein advancing the compression translator while outputting a fill bit within the relevant code word.