Circuit arrangement for the recognition of static and dynamic faults in circuit assemblies

Claim 1

In a circuit arrangement for the recognition of faults occurring in circuit assemblies, the faults being indicated by these circuit assemblies in each case by the emission of a fault signal, which faults detected by a detector means may be either static faults persisting for more than a predetermined first time period or dynamic faults which do not exceed a predetermined second time period, the fault signals being recognized at a central control unit, which central control unit is connected to these circuit assemblies and drives them for the emission of data signals including the fault signals, the improvement wherein the said central control unit has a first interrupt input that the central control unit activates when the circuit assemblies are in a fault-free state in which a fault recognition circuit emits no fault signal and a second interrupt input, having a higher interrupt priority than the first interrupt input, which the central control unit deactivates when the circuit assemblies are in the said fault-free state; a register is provided, into which register, when the circuit assemblies are driven to emit the data signals, address information with regard to the just driven circuit assembly by the central control unit is written; at least one such fault recognition circuit is provided, which, when a fault exists in a respective circuit assembly, emits a fault signal when that circuit assembly is driven; and a control device is connected to the first and second interrupt inputs of the central control unit, which, in response to such a fault signal, effects, through the first interrupt input, the performance of a first interrupt routine in the central control unit, which first interrupt routine serves to determine the presence of dynamic faults, in the course of which first interrupt routine, the central control unit activates the second interrupt input and again drives the circuit assembly designated by the address stored in the said register, and the control device effects, in the event that the said fault recognition circuit again emits a fault signal, the performance of a second interrupt routine, which serves to determine the presence of static faults and interrupts the performance of the said first interrupt routine.