Patent US4620116A successfully refreshed from Google Patents.
US4620116A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoder circuit with setting function of an output level
Assignee: NEC Electronics Corp
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Filing: 1983-10-25
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Granted: 1986-10-28
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Expires: 2003-10-25
Abstract
Abstract A decoder circuit for use in a semiconductor member device or the like as a first metal insulator semiconductor field effect transistor (MISFET) acting as a load element, a plurality of parallel-connected MISFETs controlled by the output signals of an address buffer circuit serving as driver signals. Another MISFET is connected between the first MISFET and the parallel-connected MISFETS having a control signal applied to its gate. An output is taken from the junction between the first MISFET and the MISFET connected between the first MISFET and parallel-connected MISFETs. The decoder can generate an output signal regardless of the logic states of the input signals thereto.
Inventors
- 👤 Takashi Ozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; G; G11; G11C; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
175 words
A decoder circuit comprising a first voltage terminal, a second voltage terminal, and an output terminal; a first field effect transistor having a drain-source path coupled between said first voltage terminal and said output terminal, a second field effect transistor having one of a drain and a source coupled to said output terminal, a plurality of third field effect transistors having gates receiving input signals, drain-source paths of said third transistors being coupled between the other of the drain and source of said second transistor and second voltage terminal, control means for continuously rendering said second transistor conductive in a first operating mode and rendering said second transistor non-conductive in a second operation mode, and means for enabling said first transistor in both of said first and second operating modes, wherein a level of said output terminal is determined by said input signals in said first operating mode while a level of said output terminal is set at the level of said first voltage terminal irrespective of said input signals in said second operating mode.
Claim 2
Dependent Claim
175 words
A decoder circuit comprising a first voltage terminal, a second voltage terminal, and an output terminal; a first field effect transistor having a drain-source path coupled between said first voltage terminal and said output terminal, a second field effect transistor having one of a drain and a source coupled to said output terminal, a plurality of third field effect transistors having gates receiving input signals, drain-source paths of said third transistors being coupled between the other of the drain and source of said second transistor and second voltage terminal, control means for continuously rendering said second transistor conductive in a first operating mode and rendering said second transistor non-conductive in a second operation mode, and means for enabling said first transistor in both of said first and second operating modes, wherein a level of said output terminal is determined by said input signals in said first operating mode while a level of said output terminal is set at the level of said first voltage terminal irrespective of said input signals in said second operating mode.
Claim 3
Dependent Claim
24 words
The decoder circuit according to claim 1, wherein said first transistor is of a depletion type having a gate coupled to said output terminal.
Claim 4
Dependent Claim
172 words
A decoder circuit for a clearable RAM comprising a plurality of decoders for selecting a row or column of an array of memory cells, each decoder having a first MISFET constituting a load circuit connected between a power source terminal and an output terminal; a plurality of second MISFETS connected in parallel, either the sources or the drains of which are commonly connected to reference terminals and the others of which are commonly connected to a first junction point, and arranged to have input signals applied to the gate terminals; and a third MISFET having the drain-source path connected between said output terminal and first junction point and arranged to have a first control signal applied to the gate terminal, wherein one of the rows or columns is selected by an input signal from an address circuit when the third MISFETs are being turned on by the first control signal commonly transmitted to the decoders, and all of the rows and/or columns are selected when the third MISFETs are being turned off.
Claim 5
Dependent Claim
172 words
A decoder circuit for a clearable RAM comprising a plurality of decoders for selecting a row or column of an array of memory cells, each decoder having a first MISFET constituting a load circuit connected between a power source terminal and an output terminal; a plurality of second MISFETS connected in parallel, either the sources or the drains of which are commonly connected to reference terminals and the others of which are commonly connected to a first junction point, and arranged to have input signals applied to the gate terminals; and a third MISFET having the drain-source path connected between said output terminal and first junction point and arranged to have a first control signal applied to the gate terminal, wherein one of the rows or columns is selected by an input signal from an address circuit when the third MISFETs are being turned on by the first control signal commonly transmitted to the decoders, and all of the rows and/or columns are selected when the third MISFETs are being turned off.
Claim 6
Dependent Claim
39 words
A decoder circuit according to claim 3, wherein said load circuit comprises a depletion-type MISFET wherein the drain terminal is connected to the power source terminal, and the source and gate terminals are commonly connected to the output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |