Method of manufacturing a semiconductor device and device manufactured by the use of the method

Claim 1

A method of manufacturing a semiconductor device having a plurality of adjacent narrow, closely spaced coplanar silicon electrodes, said method comprising the steps of: (a) depositing on an electrically insulating layer successively a first silicon layer, an oxidation preventing layer, and a second silicon layer; (b) etching said second silicon layer in a pattern comprising a plurality of parallel silicon strips separated by spacings; (c) partially oxidizing said pattern to form oxidized edge portions of said pattern; (d) selectively removing by etching parts of said oxidation preventing layer uncovered by said oxidized pattern; (e) selectively removing said oxidized edge portions by etching to expose edges of said oxidation preventing layer projecting from under said parallel silicon strips; (f) applying a first mask to cover said pattern including said spacings except for an area to be situated over a connection region of said first silicon layer; (g) removing exposed projecting edges of said oxidation preventing layer by etching in said connection region, and removing said first mask thereafter; (h) oxidizing exposed portion of said first silicon layer in strip-shaped parts of said first silicon layer, said strip-shaped parts being alternately covered by an oxide layer and by said oxidation preventing layer; (i) applying a second mask over said strip-shaped parts of said first silicon layer and over parts of said first silicon layer to be maintained for interconnections, and etching away unmasked parts of said second silicon layer; (j) removing selectively exposed parts of said oxidation preventing layer including said exposed projecting edges, and then removing underlying parts of said first silicon layer to form silicon electrodes separated by grooves, said silicon electrodes comprising at least one group of three adjacent parallel silicon electrodes interconnected by said connection region; (k) filling said grooves at least in part with oxide by thermal oxidation; (l) separating, in said at least one group, two of said three adjacent silicon electrodes from said connection region and a remaining electrode of said one group by etching to remove selectively area of said first silicon layer; (m) providing a contact window inside said connection region by selective etching of a layer covering said remaining electrode by using an etching mask overlapping at least one adjacent silicon electrode in a self-aligned manner; and (n) providing said two silicon electrodes of said group with contact with windows by selectively etching a layer covering said other two electrodes in a self-aligned manner.

Claim 2

A method of manufacturing a semiconductor device having a plurality of adjacent narrow, closely spaced coplanar silicon electrodes, said method comprising the steps of: (a) depositing on an electrically insulating layer successively a first silicon layer, an oxidation preventing layer, and a second silicon layer; (b) etching said second silicon layer in a pattern comprising a plurality of parallel silicon strips separated by spacings; (c) partially oxidizing said pattern to form oxidized edge portions of said pattern; (d) selectively removing by etching parts of said oxidation preventing layer uncovered by said oxidized pattern; (e) selectively removing said oxidized edge portions by etching to expose edges of said oxidation preventing layer projecting from under said parallel silicon strips; (f) applying a first mask to cover said pattern including said spacings except for an area to be situated over a connection region of said first silicon layer; (g) removing exposed projecting edges of said oxidation preventing layer by etching in said connection region, and removing said first mask thereafter; (h) oxidizing exposed portion of said first silicon layer in strip-shaped parts of said first silicon layer, said strip-shaped parts being alternately covered by an oxide layer and by said oxidation preventing layer; (i) applying a second mask over said strip-shaped parts of said first silicon layer and over parts of said first silicon layer to be maintained for interconnections, and etching away unmasked parts of said second silicon layer; (j) removing selectively exposed parts of said oxidation preventing layer including said exposed projecting edges, and then removing underlying parts of said first silicon layer to form silicon electrodes separated by grooves, said silicon electrodes comprising at least one group of three adjacent parallel silicon electrodes interconnected by said connection region; (k) filling said grooves at least in part with oxide by thermal oxidation; (l) separating, in said at least one group, two of said three adjacent silicon electrodes from said connection region and a remaining electrode of said one group by etching to remove selectively area of said first silicon layer; (m) providing a contact window inside said connection region by selective etching of a layer covering said remaining electrode by using an etching mask overlapping at least one adjacent silicon electrode in a self-aligned manner; and (n) providing said two silicon electrodes of said group with contact with windows by selectively etching a layer covering said other two electrodes in a self-aligned manner.