Address data accessing device in a rotary recording medium reproducing apparatus

Claim 1

An address data accessing device in a reproducing apparatus which reproduces recorded signals from a rotary recording medium, said rotary recording medium being time-sequentially recorded with a plurality of channels of information signals, a time address signal and a chapter address signal, said reproducing apparatus having a predetermined mode in which only reproduced information signals in selected channels out of the plurality of channels are produced, each of the information signals in the respective channels being recorded in terms of different programs, said time address signal indicating a time required in a normal reproducing mode to reach a signal recorded position on said rotary recording medium from a starting position where recording of the programs is started at the time of the recording, said chapter address signal indicating each of the different programs, said address data accessing device comprising: an output switching circuit for selectively outputting only the reproduced information signals in the selected channels out of the plurality of channels in the predetermined mode; an address data fetch circuit for fetching as an address signal one of the time address signal and the chapter address signal which are reproduced from said rotary recording medium; an instruction decoder for controlling said output switching circuit and said address data fetch circuit in response to an instruction signal which is supplied to said instruction decoder, said instruction signal comprising two bits for representing four instruction codes, two of said four instruction codes being used for selecting certain channels out of the plurality of channels, the remaining two instruction codes being used for determining which one of the time address signal and the chapter address signal is to be fetched; and a switch circuit for switching output signals of said instruction decoder in response to a switching signal from said address data fetch circuit and for supplying one output signal thereof to said address data fetch circuit, said address data fetch circuit alternately fetching and producing said time address signal and said chapter address signal to transmit the address signals under control of the one output signal of said switch circuit so that either one of said time address signal and said chapter address signal is obtainable in said predetermined mode.