Patent US4618882A successfully refreshed from Google Patents.
US4618882A
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Digital correlation indicator and hanging dot reduction system employing same
Assignee: RCA Licensing Corp
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Filing: 1985-04-18
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Granted: 1986-10-21
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Expires: 2005-04-18
Abstract
Abstract In a color TV receiver, a first digital signal of "m" bits represents high frequency component of combed luminance signal, and a second digital signal of "m" bits represents combed chrominance component. The "k" most significant bits of the first signal (where "k" is less than "m") are fed to respective inputs of a first "or" gate, while the "j" most significant bits of the second signal (where "j" is less than, or equal to, "m") are fed to respective inputs of a second "or" gate. The "or" gate outputs are fed, without delay difference, to inputs of a first "and" gate, and are fed, with a delay difference of 90° at color subcarrier frequency, to inputs of a second "and" gate. Sequence recognition apparatus, responsive to the outputs of both "and" gates, develops a correlation indication in response to existence of predetermined sequences of outputs from one or both "and" gates. Control signal former, responsive to correlation indication, forms control signal for actuating high frequency component suppression in receiver's luminance channel to preclude hanging dot display.
Inventors
- 👤 Leopold A. Harwood
- 👤 Danny Chin
- 👤 Kirk A. Law
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:37
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/77; H04N9/78
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
229 words
In a video signal processing apparatus including a source of a first digital signal of "m" bits representative of a first bipolar signal component, and a second digital signal of "m" bits representative of a second bipolar signal component, a digital correlation indicator comprising: first logic circuit means, responsive to only the "k" most significant bits of said first digital signal, where "k" is less than "m", for outputting a "1" whenever said first digital signal is representative of an excursion of said first bipolar signal component, in either a positive or a negative direction, which equals or exceeds a threshold determined by the "k'th" most significant bit of said first digital signal; second logic circuit means, responsive to only the "j" most significant bits of said second digital signal, where "j" is less than or equal to "m", for outputting a "1" whenever said second digital signal is representative of an excursion of said second bipolar signal component, in either a positive or a negative direction, which equals or exceeds a threshold determined by the "j'th" most significant bit of said second digital signal; an "and" gate having two inputs, one responsive to the output of said first logic circuit means and the other responsive to the output of said second logic circuit means and correlation indication signal developing means responsive to the output of said "and" gate.
Claim 2
Dependent Claim
229 words
In a video signal processing apparatus including a source of a first digital signal of "m" bits representative of a first bipolar signal component, and a second digital signal of "m" bits representative of a second bipolar signal component, a digital correlation indicator comprising: first logic circuit means, responsive to only the "k" most significant bits of said first digital signal, where "k" is less than "m", for outputting a "1" whenever said first digital signal is representative of an excursion of said first bipolar signal component, in either a positive or a negative direction, which equals or exceeds a threshold determined by the "k'th" most significant bit of said first digital signal; second logic circuit means, responsive to only the "j" most significant bits of said second digital signal, where "j" is less than or equal to "m", for outputting a "1" whenever said second digital signal is representative of an excursion of said second bipolar signal component, in either a positive or a negative direction, which equals or exceeds a threshold determined by the "j'th" most significant bit of said second digital signal; an "and" gate having two inputs, one responsive to the output of said first logic circuit means and the other responsive to the output of said second logic circuit means and correlation indication signal developing means responsive to the output of said "and" gate.
Claim 3
Dependent Claim
124 words
Apparatus in accordance with claim 1 wherein said correlation indication signal developing means includes: signal delay means having a plurality of successive signal takeoff points; the amount of delay between successive ones of said takeoff points being the same; the input of said delay means being responsive to the output of said "and" gate; a plurality of signal paths, each connected to a respectively different one of said signal takeoff points; a second "and" gate having a plurality of inputs equal in number to said plurality of signal paths, each of said signal paths terminating at a respectively different one of said plurality of inputs of said second "and" gate; and a control signal former responsive to the output of said second "and" gate.
Claim 4
Dependent Claim
121 words
Apparatus in accordance with claim 2 wherein said control signal former includes a succession of two-input "or" gates and a plurality of delay devices, with one input of each "or" gate of said succession rendered responsive to the output of said second "and" gate, with the output of each of said succession of "or" gates, with the exception of the last of said succession, being coupled via a respective one of said plurality of delay devices to the other input of the next succeeding one of said succession of "or" gates, and with said control signal appearing at the output of the last of said succession of "or" gates wherein each of said delay devices imparts the same amount of delay.
Claim 5
Dependent Claim
166 words
A digital correlation indicator in accordance with claim 3, for use in a color television receiver employing a system for processing composite color television signals appearing in a digital format, said composite color television signals being inclusive of a luminance signal component and a chrominance signal component comprising sidebands developed by the modulation of a color subcarrier of a frequency f sc , said system including comb filter apparatus for developing a first comb filtered signal representing composite signals subjected to a first comb filter characteristic exhibiting a plurality of response peaks at even multiples of half the line frequency of said composite signals, and a second comb filtered signal representing composite signals subjected to a second comb filter characteristic exhibiting a plurality of response peaks at odd multiples of half said line frequency; wherein said first bipolar signal component comprises high frequency components of said first comb filtered signal and said second bipolar signal component comprises high frequency components of said second comb filtered signal.
Claim 6
Dependent Claim
29 words
Apparatus in accordance with claim 4 also including means for subjecting said first comb filtered signal to high frequency component removal in response to development of said control signal.
Claim 7
Dependent Claim
62 words
Apparatus in accordance with claim 5 wherein said signal processing system is subject to clocking at a 4 f sc rate, wherein each of said delay devices imparts a delay equal to a period at 4f sc , and wherein the amount of delay between successive ones of said signal takeoff points corresponds to twice a period at 4 f sc .
Claim 8
Dependent Claim
76 words
Apparatus in accordance with claim 6 including a third "and" gate having two inputs, a pair of additional signal paths respectively linking the outputs of said first and second logic circuit means with the respective inputs of said third "and" gate, said additional signal paths exhibiting a difference in signal delay corresponding to a period at 4f sc ; the input of said delay means being additionally responsive to the output of said third "and" gate.
Claim 9
Dependent Claim
53 words
Apparatus in accordance with claim 7 wherein the input of said delay means receives signals from the output of an additional "or" gate, said additional "or" gate having a first input coupled to the output of said first-named "and" gate, and a second input coupled to the output of said third "and" gate.
Claim 10
Dependent Claim
23 words
Apparatus in accordance with claim 8 wherein the other input of the first of said succession of two-input "or" gates is effectively inactive.
Claim 11
Dependent Claim
37 words
Apparatus in accordance with claim 9 wherein the sum of the delays imparted by said plurality of delay devices exceeds the amount of delay between the first and last of said plurality of successive signal takeoff points.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |