Integrated power switching semiconductor devices including IGT and MOSFET structures

Claim 1

An integrated power switching semiconductor device comprising: a body of semiconductor material including an insulated-gate transistor portion and an insulated-gate field-effect transistor portion, said body having first and second opposed principal surfaces on opposite sides thereof; a first base layer of one conductivity type common to both said insulated-gate transistor portion and said insulated-gate field-effect transistor portion; a first main terminal region adjacent said first base layer and extending to said first principal surface, said first main terminal region including at least a portion heavily-doped to a conductivity type opposite to the conductivity type of said one conductivity and defining a PN junction with said first base layer within said insulated gate transistor portion, and said first base layer and said first main terminal region including structure for avoiding bipolar conduction within said insulated-gate field-effect transistor portion; a second base region of the opposite conductivity type and having two portions contiguous with said first base layer, one of said portions of said second base region being included in said insulated gate transistor portion and the other of said portions of said second base region being included in said insulated-gate field-effect transistor portion; a first region of the one conductivity type being included in said insulated-gate transistor portion contiguous with said one portion of said second base region; a second region of the one conductivity type included in said insulated-gate field-effect transistor portion contiguous with said other portion of said second base region; a second terminal overlying at least a portion of said second base region and said first region and being in contact therewith; a first channel region included in said insulated-gate transistor portion within said first region of the one conductivity type, and a second channel region included in said insulated-gate fieldeffect transistor portion within said second region of the one conductivity type, said first and second regions of the one conductivity type being spaced from the respective portions of said first base layer to define the extent of the respective channel regions therebetween; first and second gate electrodes respectively disposed over said first and second channel regions and insulatingly spaced therefrom, said gate electrodes configured for inducing, when gate voltage is applied thereto, respective conduction paths of the one conductivity type in the respective channel regions beneath the respective energized gate electrodes; a resistance element connected between said first and second gate electrodes; and a device gate conductor connected directly to one of said gate electrodes and to the other of said gate electrodes by said resistive element.