Erasable FPLA

Claim 2

A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an AND plane including a plurality of AND gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals; and an OR plane including a plurality of OR gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of AND gates in said AND plane and to supply a logic output, wherein at least one of said AND and OR planes includes: a matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.

Claim 3

A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an AND plane including a plurality of AND gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals; and wherein said AND plane includes: a matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.

Claim 4

A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an AND plane including a plurality of AND gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals; and wherein said AND plane includes: a matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.

Claim 5

A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an OR plane including a plurality of OR gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals and to supply a logic output, wherein said OR plane includes: matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.

Claim 6

A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an OR plane including a plurality of OR gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals and to supply a logic output, wherein said OR plane includes: matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.

Claim 7

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a first plurality of conductors and a second plurality of conductors extending in the direction normal to and electrically isolated from said first conductors; a plurality of input terminals connected to said matrix; a plurality of output terminals connected to said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said first and second pluralities of conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding first conductor, its second electrode connected to the corresponding second conductor and its third electrode connected to a reference voltage; wherein each conductor is one of said first and second pluralities of conductors and the reprogrammable memory elements associated therewith form one gate of said logic function.

Claim 8

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a first plurality of conductors and a second plurality of conductors extending in the direction normal to and electrically isolated from said first conductors; a plurality of input terminals connected to said matrix; a plurality of output terminals connected to said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said first and second pluralities of conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding first conductor, its second electrode connected to the corresponding second conductor and its third electrode connected to a reference voltage; wherein each conductor is one of said first and second pluralities of conductors and the reprogrammable memory elements associated therewith form one gate of said logic function.

Claim 9

A programmable logic array according to claim 4 wherein said logic function is the AND function.

Claim 10

A programmable logic array according to claim 4 wherein said logic function is the OR function.

Claim 11

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a plurality of horizontal conductors which may be selectively connected to a first reference voltage and a plurality of vertical conductors extending in the direction normal to and electrically isolated from said horizontal conductors; a plurality of input terminals each of which is connected to supply one binary state to the corresponding one of said vertical conductors of said matrix and the other binary state to the other corresponding one of said vertical conductors of said matrix; a plurality of output terminals connected to receive output signals from the horizontal conductors of said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said horizontal and vertical conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding vertical conductor, its second electrode connected to the corresponding horizontal conductor and its third electrode connected to a reference voltage; wherein each horizontal conductor and the programmable memory elements associated therewith form one gate of said logic function.

Claim 12

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a plurality of horizontal conductors which may be selectively connected to a first reference voltage and a plurality of vertical conductors extending in the direction normal to and electrically isolated from said horizontal conductors; a plurality of input terminals each of which is connected to supply one binary state to the corresponding one of said vertical conductors of said matrix and the other binary state to the other corresponding one of said vertical conductors of said matrix; a plurality of output terminals connected to receive output signals from the horizontal conductors of said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said horizontal and vertical conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding vertical conductor, its second electrode connected to the corresponding horizontal conductor and its third electrode connected to a reference voltage; wherein each horizontal conductor and the programmable memory elements associated therewith form one gate of said logic function.

Claim 13

A programmable logic array according to claim 7 wherein said logic function is the AND function.

Claim 14

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a plurality of horizontal conductors and a plurality of vertical conductors extending in the direction normal to and electrically isolated from said horizontal conductors of said matrix; a plurality of input terminals connected to said horizontal conductors; output terminals connected to receive output signals from the vertical conductors of said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said horizontal and vertical conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding horizontal conductor, its second electrode connected to the corresponding vertical conductor and its third electrode connected to a reference voltage; wherein each vertical conductor and the programmable memory elements associated therewith form one gate of said logic function.

Claim 15

A programmable logic array in which a desired logic function may be erasably programmed comprising: a matrix of conductors including a plurality of horizontal conductors and a plurality of vertical conductors extending in the direction normal to and electrically isolated from said horizontal conductors of said matrix; a plurality of input terminals connected to said horizontal conductors; output terminals connected to receive output signals from the vertical conductors of said matrix; a plurality of reprogrammable memory elements each disposed at the cross-over point between said horizontal and vertical conductors, each of said reprogrammable memory elements disposed in said matrix having its first electrode connected to the corresponding horizontal conductor, its second electrode connected to the corresponding vertical conductor and its third electrode connected to a reference voltage; wherein each vertical conductor and the programmable memory elements associated therewith form one gate of said logic function.

Claim 16

A programmable logic array according to claim 9 wherein said logic function is the OR function.

Claim 17

A programmable logic array according to claim 1, further comprising: means for applying a predetermined potential to said first conductors.

Claim 18

A programmable logic array according to claim 11, wherein said predetermined potential is a supply voltage.

Claim 19

A programmable logic array according to claim 12 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain/source connected to a corresponding one of said first conductors and a gate connected to said corresponding one of said first conductors.

Claim 20

A programmable logic array according to claim 13, wherein said MOSFET is a depletion-mode MOSFET.

Claim 21

A programmable logic array according to claim 2, further comprising: means for applying a predetermined potential to said first conductors.

Claim 22

A programmable logic array according to claim 15, wherein said predetermined potential is a supply voltage.

Claim 23

A programmable logic array according to claim 16 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain/source connected to a corresponding one of said first conductors and a gate connected to said corresponding one of said first conductors.

Claim 24

A programmable logic array according to claim 17, wherein said MOSFET is a depletion-mode MOSFET.

Claim 25

A programmable logic array according to claim 3, further comprising: means for applying a predetermined potential to said first conductors.

Claim 26

A programmable logic array according to claim 19, wherein said predetermined potential is a supply voltage.

Claim 27

A programmable logic array according to claim 20 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain/source connected to a corresponding one of said first conductors and a gate connected to said corresponding one of said first conductors.

Claim 28

A programmable logic array according to claim 21, wherein said MOSFET is a depletion mode MOSFET.

Claim 29

A programmable logic array according to claim 4, further comprising: means for applying a predetermined potential to said first plurality of conductors.

Claim 30

A programmable logic array according to claim 23, wherein said predetermined potential is a supply voltage.

Claim 31

A programmable logic array according to claim 24 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain/source connected to a corresponding one of said first plurality of conductors and a gate connected to said corresponding one of said first plurality of conductors.

Claim 32

A programmable logic array according to claim 25, wherein said MOSFET is a depletion-mode MOSFET.

Claim 33

A programmable logic array according to claim 7, further comprising: means for applying a predetermined potential to said horizontal conductors.

Claim 34

A programmable logic array according to claim 27 wherein said predetermined potential is a supply voltage.

Claim 35

A programmable logic array according to claim 28 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain/source connected to a corresponding one of said horizontal conductors and a gate connected to said corresponding one of said horizontal conductors.

Claim 36

A programmable logic array according to claim 29, wherein said MOSFET is a depletion-mode MOSFET.

Claim 37

A programmable logic array according to claim 9, further comprising: means for applying a predetermined potential to said horizontal conductors.

Claim 38

A programmable logic array according to claim 31, wherein said predetermined potential is a supply voltage.

Claim 39

A programmable logic array according to claim 32 wherein said means for applying includes at least one MOSFET having a first drain/source connected to said supply voltage, a second drain source connected to a corresponding one of said horizontal conductors and a gate connected to said corresponding one of said horizontal conductors.

Claim 40

A programmable logic array according to claim 33, wherein said MOSFET is a depletion-mode MOSFET.