Patent US4617648A successfully refreshed from Google Patents.
US4617648A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1984-11-08
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Granted: 1986-10-14
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Expires: 2004-11-08
Abstract
Abstract A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.
Inventors
- 👤 Shigeo Kuboki
- 👤 Hideo Maejima
- 👤 Ikuro Masuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:48
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; H; H10; H10D; H10D84/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; H10P; H10P74/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, said device comprising: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with said flip-flop circuit, when said semiconductor integrated circuit device is diagnosed to detect a fault therein; second means connected to the output side of said flip-flop circuit for making and breaking the closed loop of said gates in accordance with said first write timing signal; third means connected to the output side of said flip-flop circuit for supplying said diagnostic data to said flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of said flip-flop circuit for blocking a signal applied to the input side of said flip-flop circuit, in accordance with said diagnosis control signal.
Claim 2
Dependent Claim
159 words
A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, said device comprising: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with said flip-flop circuit, when said semiconductor integrated circuit device is diagnosed to detect a fault therein; second means connected to the output side of said flip-flop circuit for making and breaking the closed loop of said gates in accordance with said first write timing signal; third means connected to the output side of said flip-flop circuit for supplying said diagnostic data to said flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of said flip-flop circuit for blocking a signal applied to the input side of said flip-flop circuit, in accordance with said diagnosis control signal.
Claim 3
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 1, wherein said second means includes a clocked NOR gate, said third means includes a clocked inverter, and said fourth means includes an AND gate.
Claim 4
Dependent Claim
32 words
A semiconductor integrated circuit device according to claim 1, wherein said second means includes an NMOS transistor, said third means includes a clocked inverter, and said fourth means includes an OR gate.
Claim 5
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 1, wherein said second means includes a clocked NAND gate, said third means includes a clocked inverter, and said fourth means includes an NAND gate and an OR gate.
Claim 6
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 4, wherein said third means further includes a variable-resistance element.
Claim 7
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 1, wherein said flip-flop circuit further includes a combinational circuit.
Claim 8
Dependent Claim
35 words
A semiconductor integrated circuit device according to claim 1, further comprising a read flip-flop circuit connected to the output side of said flip-flop circuit for holding and reading out the output of said flip-flop circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-13 | 1990-04-14 | 1990-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-13 | 1994-04-14 | 1994-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-13 | 1998-04-14 | 1998-10-14 | $7700.00 | Window Closed / Lapsed |