US4617478A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Emitter coupled logic having enhanced speed characteristic for turn-on and turn-off
Assignee: RPX Corp
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Filing: 1983-09-07
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Granted: 1986-10-14
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Expires: 2003-09-07
Abstract
Abstract In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q A is switched on or off significantly faster.
Inventors
- 👤 Hemmige D. Varadarajan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
112 words
A device for switching current, comprising: a common node connected to receive the current; an output node connectable to provide an output; a least one input transistor having a collector connected to said output node, an emitter connected to said common node, and a base connected to receive at least one input signal; and reference means connected to said common node for supplying a switching bias at said common node, including means for filtering high frequency voltage change at said common node, wherein said filtering means includes a transistor having a base connected to a bias voltage, an emitter connected to a supply voltage and a collector connected to said common node.
Claim 2
Independent Claim
112 words
A device for switching current, comprising: a common node connected to receive the current; an output node connectable to provide an output; a least one input transistor having a collector connected to said output node, an emitter connected to said common node, and a base connected to receive at least one input signal; and reference means connected to said common node for supplying a switching bias at said common node, including means for filtering high frequency voltage change at said common node, wherein said filtering means includes a transistor having a base connected to a bias voltage, an emitter connected to a supply voltage and a collector connected to said common node.
Claim 3
Dependent Claim
128 words
A digital logic gate for switching current, comprising: a common node connected to receive the current; an output node connectable to provide an output; at least one input transistor having a collector connected to said output node, an emitter connected to said common node, and a base connected to receive at least one input signal; and reference means connected to said common node for supplying a switching reference at said common node, including a reference transistor having a base connected to a bias voltage, an emitter coupled to a supply voltage, and a collector coupled to said common node; wherein said at least one input transistor is one of an NPN bipolar type transistor or a PNP bipolar type transistor, and said reference transistor is said one type.
Claim 4
Dependent Claim
128 words
A digital logic gate for switching current, comprising: a common node connected to receive the current; an output node connectable to provide an output; at least one input transistor having a collector connected to said output node, an emitter connected to said common node, and a base connected to receive at least one input signal; and reference means connected to said common node for supplying a switching reference at said common node, including a reference transistor having a base connected to a bias voltage, an emitter coupled to a supply voltage, and a collector coupled to said common node; wherein said at least one input transistor is one of an NPN bipolar type transistor or a PNP bipolar type transistor, and said reference transistor is said one type.
Claim 5
Dependent Claim
26 words
The device of claim 1 or 2, further including an emitter follower output circuit coupled to said output node to form an emitter coupled logic gate.
Claim 6
Dependent Claim
105 words
The digital logic gate of claim 2, wherein: said at least one input transistor has a base-to-emitter junction, an RC combination of a dynamic resistance and a diffusion capacitance of the base-to-emitter junction of the at least one input transistor and an input time constant representing the RC combination; and said reference transistor has a collector-to-emitter junction, an RC combination of a dynamic resistance and a diffusion capacitance of the collector-to-base junction of the reference transistor, and a time constant representing the RC combination that is at least an order to magnitude greater than the input time constant of the at least one input transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-13 | 1990-04-14 | 1990-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-13 | 1994-04-14 | 1994-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-13 | 1998-04-14 | 1998-10-14 | $7700.00 | Window Closed / Lapsed |