US4538075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed referenceless bipolar logic gate with minimum input current
Assignee: RPX Corp
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Filing: 1983-09-07
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Granted: 1985-08-27
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Expires: 2003-09-07
Abstract
Abstract In a logic gate which is provided having input transistors each with a collector electrode at a first node (which serves as a signal output node), an emitter electrode at a second node to which all emitters are coupled and a base electrode for receiving binary logic signal input, and further having a load resistor between the first node and a supply voltage coupling, the improvement in that means are provided for controlling the emitter current at the second node in response to voltage on the first node in order to inhibit saturation of the input transistors and to enhance switching speed of the logic gate. The emitter current controlling means may include a current regulating transistor coupled between the second node and a ground reference wherein the base electrode thereof is coupled through a third node to a biasing means coupled to the first node. The current regulating transistor may be a Schottky transistor, that is, a transistor with a Schottky diode coupled between the base electrode and the collector electrode. The biasing means may be a feedback resistor coupled between the first node and the third node. Voltage across the feedback resistor may be clamped to limit voltage range.
Inventors
- 👤 Hemmige D. Varadarajan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
140 words
A logic gate having at least one input transistor means, each said input transistor means having a collector electrode connected to a first node, said first node being an output signal node, an emitter electrode connected to a second node and a base electrode for receiving binary logic signal input, and said gate further having a load resistor between said first node and a supply voltage terminal, the improvement comprising: means coupled to said second node and responsive to the voltage on said first node for controlling emitter current of said input transistor means through said second node to inhibit saturation of said input transistor means; and means coulpled to said first node, and further coupled to said emitter current controlling means, for limiting the output voltage of said logic gate by clamping said output voltage to a maximum value.
Claim 2
Dependent Claim
140 words
A logic gate having at least one input transistor means, each said input transistor means having a collector electrode connected to a first node, said first node being an output signal node, an emitter electrode connected to a second node and a base electrode for receiving binary logic signal input, and said gate further having a load resistor between said first node and a supply voltage terminal, the improvement comprising: means coupled to said second node and responsive to the voltage on said first node for controlling emitter current of said input transistor means through said second node to inhibit saturation of said input transistor means; and means coulpled to said first node, and further coupled to said emitter current controlling means, for limiting the output voltage of said logic gate by clamping said output voltage to a maximum value.
Claim 3
Dependent Claim
59 words
A logic gate according to claim 1 wherein said emitter current controlling means comprises a current regulating transistor means having a collector electrode coupled to said second node, an emitter electrode coupled to a ground reference terminal and a base electrode coupled through a third node to a biasing means, said biasing means being coupled to said first node.
Claim 4
Dependent Claim
42 words
A logic gate according to claim 2 wherein said current controlling means further includes a first Schottky diode having a cathode electrode coupled to said second node and an anode electrode coupled to said third node, said transistor means being NPN transistors.
Claim 5
Dependent Claim
61 words
A logic gate according to claim 3 wherein said biasing means comprises a feedback resistor, said feedback resistor being coupled between said first node and said third node such that a change in voltage level at said first node causes a controlled change in voltage level and current at said third node to control base current to said current regulating transistor.
Claim 6
Dependent Claim
42 words
The logic gate according to claim 1 wherein said means for limiting the output voltage of said logic gate is a second Schottky diode having an anode electrode coupled to said first node and a cathode electrode coupled to said third node.
Claim 7
Dependent Claim
53 words
The logic gate according to claim 1 wherein said logic signal input is restricted to a range of about a base-emitter voltage drop of a bipolar junction transistor when forward biased (V BE ) to about V BE + a voltage drop across a Schottky barrier diode during conduction state (V SBD ).
Claim 8
Dependent Claim
145 words
A logic gate having at least one input transistor means, each said input transistor means having a collector electrode connected to a first node, said first node being an output signal node, an emitter electrode connected to a second node and a base electrode for receiving binary logic signal input, and said gate further having a load resistor between said first node and a supply voltage terminal, the improvement comprising: means coupled to said second node and responsive to the voltage on said first node for controlling emitter current of said input transistor means through said second node to inhibit saturation of said input transistor means; and biasing means coupled through a third node to said emitter current controlling means and further coupled to said first node, for limiting the output voltage of said logic gate by clamping said output voltage to a maximum value.
Claim 9
Dependent Claim
145 words
A logic gate having at least one input transistor means, each said input transistor means having a collector electrode connected to a first node, said first node being an output signal node, an emitter electrode connected to a second node and a base electrode for receiving binary logic signal input, and said gate further having a load resistor between said first node and a supply voltage terminal, the improvement comprising: means coupled to said second node and responsive to the voltage on said first node for controlling emitter current of said input transistor means through said second node to inhibit saturation of said input transistor means; and biasing means coupled through a third node to said emitter current controlling means and further coupled to said first node, for limiting the output voltage of said logic gate by clamping said output voltage to a maximum value.
Claim 10
Dependent Claim
88 words
A logic gate according to claim 7 wherein said emitter current controlling means comprises: a current regulating transistor means having a collector electrode coupled to said second node, an emitter electrode coupled to a ground reference coupling and a base electrode coupled through a third node to a biasing means, said biasing means being coupled to said first node; and a first Schottky diode having a cathode electrode coupled to said second node and an anode electrode coupled to said third node, said transistor means being NPN transistors.
Claim 11
Dependent Claim
94 words
A logic gate according to claim 7 wherein said biasing means comprises: a feedback resistor, said feedback resistor being coupled between said first node and said third node such that a change in voltage level at said first node causes a controlled change in voltage level and current at said third node to control base current to said current regulating transistor; and a clamping means coupled across said feedback resistor for limiting voltage drop across said feedback resistor in order to inhibit saturation of input elements of other gates driven from said first node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-26 | 1989-02-25 | 1989-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-26 | 1993-02-25 | 1993-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-26 | 1997-02-25 | 1997-08-27 | $7700.00 | Window Closed / Lapsed |