High speed clocked, latched, and bootstrapped buffer

Claim 1

A buffer circuit for deriving, from an input signal, an output signal which is substantially synchronous with at least some of the changes in state of a first clock signal and wherein a change in logic state of the input signal causes a corresponding change in logic state of the output signal, said buffer circuit comprising: a first transistor whose main current path is connected between the first clock and the circuit output, so that the first clock drives the output directly; a second and a third transistor whose main current paths are connected in series between the circuit output and ground for pulling the output low, the first clock signal being applied to the gate of the second transistor; a fourth transistor whose main current path is connected between the input and the gate of the third transistor; a second clock for applying a second clock signal to the gate of the fourth transistor, so that the input signal is sampled within a time window determined by the second clock signal, and so that the sampled input signal is applied to the gate of the fourth transistor; a delay means for delaying the output signal; a NOR-gate receiving at its inputs the sampled input signal and the delayed output signal; a fifth transistor whose gate is supplied with a first DC voltage and whose main current path is connected between the output of the NOR-gate and the gate of the first transistor for boosting the voltage at the gate of the first transistor so that the delay between the rise times of the first clock and changes in the state of the output signals is reduced, and wherein the delayed output signal is delayed by the delay means by such time that the output signal is allowed to rise to substantially its maximum value before such rise causes the first transistor to be turned off; and means coupled to the circuit output for holding the value of the output signal when the first transistor is turned off and when the second or third transistors is turned off.