US4616406A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit layers therein
Assignee: MUTOH AMERICA Inc
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Filing: 1984-09-27
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Granted: 1986-10-14
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Expires: 2004-09-27
Abstract
Abstract An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bonding the array of parallel conductor pins directly to an integrated circuit die while maintaining the die in a plane perpendicular to the parallel pins; and surrounding the die with a package material capable of protecting the die.
Inventors
- 👤 Candice H. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:35
CPC Classifications
H; H10; H10W; H10W99/00; H10W74/00; H10W74/01; H10W74/10; H10W74/111; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49169; Y10T29/49171; Y10T29/49172
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
101 words
A method for making a semiconductor device comprising an integrated circuit die and a mounting package including leads to interconnect the die with external electrical components, said process comprising: (a) forming an array of parallel conductor pins equidistantly spaced apart hexagonal to one another to provide enhanced spacing; (b) bonding the array of parallel conductor pins directly to an array of contact pads formed on an integrated circuit die in registry with said pin array while maintaining said die in a plane perpendicular to said parallel pins; and (c) surrounding said die with a package material capable of protecting said die.
Claim 2
Independent Claim
101 words
A method for making a semiconductor device comprising an integrated circuit die and a mounting package including leads to interconnect the die with external electrical components, said process comprising: (a) forming an array of parallel conductor pins equidistantly spaced apart hexagonal to one another to provide enhanced spacing; (b) bonding the array of parallel conductor pins directly to an array of contact pads formed on an integrated circuit die in registry with said pin array while maintaining said die in a plane perpendicular to said parallel pins; and (c) surrounding said die with a package material capable of protecting said die.
Claim 3
Dependent Claim
39 words
The method of claim 1 wherein said array of parallel pins is formed by placing a plurality of equal length pins in a jig having a plurality of spaced apart parallel bores of equal depth in one surface thereof.
Claim 4
Dependent Claim
42 words
The method of claim 2 wherein the exposed ends of said pins are coated with solder and said die is then placed against said solder coated pins while heating said solder to cause said pins to be bonded perpendicular to said die.
Claim 5
Dependent Claim
39 words
The process of claim 3 wherein said die, having said pins bonded perpendicular thereto, is encapsulated in plastic to form a semiconductor device having a high density conductor pin array and further characterized by good electrical and thermal conductivity.
Claim 6
Dependent Claim
29 words
The method of claim 3 wherein said die, having said pins bonded perpendicular thereto, is sealed in a hermetically sealed case to protect said die from the external ehvironment.
Claim 7
Dependent Claim
54 words
The method of claim 5 wherein said die having said pin array bonded thereto is placed in a mold having raised portions thereon contacting the surface of said die opposite the surface having said pin array bonded thereto, and having guide members on the side walls of said mold to center said die therein.
Claim 8
Dependent Claim
25 words
The method of claim 6 wherein an elastomeric material is placed in said mold around said die to provide shock mounting support for said die.
Claim 9
Dependent Claim
30 words
The method of claim 7 wherein an encapsulating material is placed in said mold over said die and elastomeric material to seal said die and elastomeric material in said mold.
Claim 10
Dependent Claim
41 words
The method of claim 2 wherein said pins in said die are partially encapsulated in a material capable of maintaining said pins in parallel alignment upon removal from said jig with both ends of each pin exposed for electrical contact thereto.
Claim 11
Dependent Claim
59 words
The method of claim 9 wherein said die is subsequently electrically bonded to said pins by coating one end of said pins with solder and then bringing said die into contact with said solder coated pins while heating said solder to cause said die to bond to said pins in a plane normal to the axes of said pins.
Claim 12
Dependent Claim
16 words
The method of claim 1 wherein said parallel pins are spaced 25 mils apart on center.
Claim 13
Independent Claim
169 words
A method for making a semiconductor device comprising an integrated circuit die and a mounting package including leads to interconnect the die with external electrical components, said process comprising: (a) forming an array of parallel conductor pins equidistantly spaced apart hexagonal to one another to provide enhanced spacing; (b) forming one or more additional patterned layers of conductors adjacent one surface of a conventional integrated circuit die having contact points located on the periphery of said die to provide conductive paths from said peripheral conduction pads on said die to an array of contact pads on the outside surface of said one or more additional patterned layers in registry with said pin array; (c) bonding said array of parallel conductor pins directly to said array of contact pads integrally formed on the outside surface of said die in registry with said pin array while maintaining said die in a plane perpendicular to said parallel pins; and (d) surrounding said die with a package material capable of protecting said die.
Claim 14
Independent Claim
169 words
A method for making a semiconductor device comprising an integrated circuit die and a mounting package including leads to interconnect the die with external electrical components, said process comprising: (a) forming an array of parallel conductor pins equidistantly spaced apart hexagonal to one another to provide enhanced spacing; (b) forming one or more additional patterned layers of conductors adjacent one surface of a conventional integrated circuit die having contact points located on the periphery of said die to provide conductive paths from said peripheral conduction pads on said die to an array of contact pads on the outside surface of said one or more additional patterned layers in registry with said pin array; (c) bonding said array of parallel conductor pins directly to said array of contact pads integrally formed on the outside surface of said die in registry with said pin array while maintaining said die in a plane perpendicular to said parallel pins; and (d) surrounding said die with a package material capable of protecting said die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-13 | 1990-04-14 | 1990-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-13 | 1994-04-14 | 1994-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-13 | 1998-04-14 | 1998-10-14 | $7700.00 | Window Closed / Lapsed |