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Patent US4616187A successfully refreshed from Google Patents.
US4616187A
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Frequency shift keying signal for a demodulator
Assignee: NEC Corp
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Filing: 1985-07-12
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Granted: 1986-10-07
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Expires: 2005-07-12
Abstract
Abstract A frequency shift keying signal in analog form alternatively includes a mark frequency, f m , and a space frequency, f s . Demodulation of the frequency shift keying signal is achieved in a digital circuit utilizing a clock and first and second counters. Each counter may have a count N. The clock produces pulses with a frequency of 2Nf c ; where N is the count of the counters, and f c is a frequency intermediate the mark frequency, f m , and the space frequency, f s . Associated digital circuitry permits the first counter to produce an output indicative of the presence of the mark frequency only when the first counter has continuously counted N clock pulses. Further digital circuitry permits the second counter to count only intermittently, and a reset circuit resets the second counter before it can produce a high output signal when the mark frequency is present in the frequency.
Inventors
- 👤 Kyoji Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:15
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
224 words
A demodulator for a frequency shift keying signal, said demodulator comprising: signal converter means for converting an analog frequency shift keying signal having a space frequency, f s , and a higher mark frequency, f m , to a rectangular-wave signal having two wavelengths T s and T m , respectively, said wavelengths T s and T m equalling the reciprocal values of the space frequency, f s , and the mark frequency, f m , respectively; a clock means for producing digital signals at a frequency of repitition that is an integer multiple of a frequency, f c , intermediate the space frequency, f s , and the mark frequency, f m ; first counter means with a count N 1 for counting said digital clock signals and producing a first output signal indicative of the mark frequency, f m , being present in the frequency keying signal, said output signal being produced only when the counter means has continuously counted clock signals for a period of T c /2, where T c is a wavelength equalling the reciprocal of the intermediate frequency, f c ; and second counter means with a count N 2 for intermittently counting said digital clock signals and producing a second output signal indicative of the space frequency, f s , being present in the frequency keying signal.
Claim 2
Dependent Claim
224 words
A demodulator for a frequency shift keying signal, said demodulator comprising: signal converter means for converting an analog frequency shift keying signal having a space frequency, f s , and a higher mark frequency, f m , to a rectangular-wave signal having two wavelengths T s and T m , respectively, said wavelengths T s and T m equalling the reciprocal values of the space frequency, f s , and the mark frequency, f m , respectively; a clock means for producing digital signals at a frequency of repitition that is an integer multiple of a frequency, f c , intermediate the space frequency, f s , and the mark frequency, f m ; first counter means with a count N 1 for counting said digital clock signals and producing a first output signal indicative of the mark frequency, f m , being present in the frequency keying signal, said output signal being produced only when the counter means has continuously counted clock signals for a period of T c /2, where T c is a wavelength equalling the reciprocal of the intermediate frequency, f c ; and second counter means with a count N 2 for intermittently counting said digital clock signals and producing a second output signal indicative of the space frequency, f s , being present in the frequency keying signal.
Claim 3
Dependent Claim
26 words
The demodulator of claim 1, wherein the count N 1 equals one-half of the wavelength T c multiplied by the frequency of said digital clock signals.
Claim 4
Dependent Claim
46 words
The demodulator of claim 1, wherein said first counter means includes reset means for resetting the count of said first counter means for preventing the production of said first output signal when the space frequency, f s , is present in the frequency shift keying signal.
Claim 5
Dependent Claim
82 words
The demodulator of claim 3, wherein said reset means includes means for producing a signal operative to reset to zero the count of said first counter means at every alternate half-period of the rectangular-wave signal, whereby said second counter means can reach its count N 1 only when the half-period of the rectangular-wave signal exceeds the time required to reach the count N 1 which occurs only when the mark frequency, f m , is present in the frequency shift keying signal.
Claim 6
Dependent Claim
60 words
The demodulator of claim 1, wherein said second counter means includes reset means for preventing said second counter means from producing an output signal indicative of the actual attainment of the count N 2 whenever the frequency shift keying signal is at the mark frequency, f m ; said reset means being activated in response to said first output signal.
Claim 7
Dependent Claim
35 words
The demodulator of claim 5, further including a disabling means for preventing said second counter means from counting the digital clock signals during alternate half-periods of the rectangular-wave output signal of said signal converter means.
Claim 8
Dependent Claim
60 words
The demodulator of claim 1, further including memory means responsive to said first and second counter means for memorizing the first and second output signals and for alternately producing one or the other of two constant output signals indicating the presence of the mark or space frequencies, f m or f s , respectively, in the frequency shift keying signal.
References Cited (Backward Citations)
US3614639A
Cited
US3979685A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |