Patent US4614935A successfully refreshed from Google Patents.
US4614935A
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Log and antilog functions for video baseband processing
Assignee: RCA Licensing Corp
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Filing: 1984-12-24
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Granted: 1986-09-30
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Expires: 2004-12-24
Abstract
Abstract The log encoder includes means for determining a number r corresponding to the position of the most significant one in the respective input samples, and generating an equivalent binary value. To the binary value is added a predetermined value when the input samples are non-zero to generate m-bit binary values representing the m most significant bits of the output samples in the log domain. The log encoder further includes means for generating l-bit binary values corresponding to the bits to the right of the most significant one in the input samples. The m-bit binary values are concatenated with the l-bit binary values as the most and least significant bits, which concatenated values represent the output samples in the log domain. The process is essentially reversed to convert the binary values in the log domain back into the non-log domain.
Inventors
- 👤 Russell T. Fling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:14
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0307; H; H03; H03M; H03M7/00; H03M7/30; H03M7/50; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/4833; G06F7/52; G06F7/523; G06F7/5235
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
314 words
A digital signal processing apparatus for encoding n-bit binary input samples to produce m+l bit binary output samples representative of a given logarithmic function of said input samples; each of said binary input samples being represented by n binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said binary output samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; said encoding apparatus comprising: (A) an input terminal for applying said n-bit binary input samples; (B) means, coupled to said input terminal, for determining the bit position of highest significance exhibiting a logical one state in the respective one of said input samples to produce at an output thereof a first set of binary numbers corresponding to said bit position of highest significance; (C) selectively-actuated means, coupled to said bit position determining means, for adding a fixed binary value to said first set of numbers when said input samples are non-zero to produce a second set of binary numbers corresponding to the m most significant bits of said m+l bit output samples; (D) means including means, coupled to said input terminal, for generating a third set of binary numbers corresponding to the bits of lesser significance than said bit position of highest significance in said input samples; said third set of binary numbers corresponding to the l least significant bits of said m+l bit output samples; and (E) means, coupled to said selectively-actuated means and to said means for generating said third set of binary numbers, for concatenating said second and third sets of binary numbers to produce said m+l bit output samples representing a log-linear approximation of said given logarithmic function.
Claim 2
Dependent Claim
314 words
A digital signal processing apparatus for encoding n-bit binary input samples to produce m+l bit binary output samples representative of a given logarithmic function of said input samples; each of said binary input samples being represented by n binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said binary output samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; said encoding apparatus comprising: (A) an input terminal for applying said n-bit binary input samples; (B) means, coupled to said input terminal, for determining the bit position of highest significance exhibiting a logical one state in the respective one of said input samples to produce at an output thereof a first set of binary numbers corresponding to said bit position of highest significance; (C) selectively-actuated means, coupled to said bit position determining means, for adding a fixed binary value to said first set of numbers when said input samples are non-zero to produce a second set of binary numbers corresponding to the m most significant bits of said m+l bit output samples; (D) means including means, coupled to said input terminal, for generating a third set of binary numbers corresponding to the bits of lesser significance than said bit position of highest significance in said input samples; said third set of binary numbers corresponding to the l least significant bits of said m+l bit output samples; and (E) means, coupled to said selectively-actuated means and to said means for generating said third set of binary numbers, for concatenating said second and third sets of binary numbers to produce said m+l bit output samples representing a log-linear approximation of said given logarithmic function.
Claim 3
Dependent Claim
61 words
The encoding apparatus as defined in claim 1 wherein said selectively-actuated adding means comprises a plurality of AND gates, each (a) having a first input coupled for receiving the respective one of the bits of said fixed binary value, and (b) having a second input which is a logical one when said input samples are nonzero and a logical zero otherwise.
Claim 4
Dependent Claim
24 words
The encoding apparatus as defined in claim 2 wherein the second inputs of said AND gates are derived from said bit position determining means.
Claim 5
Dependent Claim
53 words
The encoding apparatus as defined in claim 2 wherein said selectively-actuated adding means further includes means for combining said first set of numbers with said output of said AND gates to produce at the output thereof said second set of binary numbers representative of the m most significant bits of said output samples.
Claim 6
Dependent Claim
87 words
The encoding apparatus as defined in claim 1 wherein said means for generating said third set of binary numbers comprises means coupled to said input terminal and to said bit position determining means for shifting said input samples toward the position of higher significance until said highest significance bit exhibiting a logical one state is displaced out of said shifting means to produce at an output thereof said third set of binary numbers associated with the said l least significant bits of said m+l bit output samples.
Claim 7
Dependent Claim
81 words
The encoding apparatus as defined in claim 5 wherein said first set of binary numbers at said output of said bit position determining means vary from 1 to n as said highest significance bit exhibiting a logical one state in said input samples shifts from said least significant bit position position to said most significant bit position position respectively; wherein said output of said bit position determining means is zero in the absence of a logical one in said input samples.
Claim 8
Dependent Claim
96 words
The encoding apparatus as defined in claim 6 further including means for inverting said first set of binary numbers to produce at an output thereof a value defining the number of shifts toward the position of higher significance necessary for transferring out said highest significance bit exhibiting a logical one state from the n-1 least significant bits of said n-bit input samples; said output of said inverting means being applied to said shifting means to generate said third set of numbrrs associated with the said l least significant bits of said m+l bit log-linear output samples.
Claim 9
Dependent Claim
108 words
The encoding apparatus as defined in claim 7 wherein said means for generating said third set of binary numbers further includes a log fixup means responsive to said l least significant bits at said output of said shifting means for correcting said least significant bits for the differences between said log-linear approximation and said given logarithmic function to produce a fourth set of binary numbers defining the l log-corrected least significant bits; said concatenating means merging said m-bit second set of most significant bits with said l-bit fourth set of log-corrected least significant bits to produce m+l bit log-corrected output samples more accurately defining said given logarithmic function.
Claim 10
Dependent Claim
90 words
The encoding apparatus as defined in claim 8 wherein said log fixup means includes a ROM which produces at the output thereof binary correction numbers corresponding to the respective differences between said log-linear approximation and said given logarithmic function in response to said third set of uncorrected least significant bits applied thereto as address codes; said log fixup means additionally having means for combining said third set of uncorrected least significant bits with said correction numbers to generate at the output thereof said fourth set of log-corrected least significant bits.
Claim 11
Dependent Claim
82 words
The encoding apparatus as defined in claim 9 wherein said log fixup means further includes a plurality of AND gates, each (a) having a first input for receiving the respective one of said correction numbers (b) having a second input which is a logical zero when said second set of numbers are all logical one's, and (c) having an output which is coupled to said combining means of said log fixup means to produce said fourth set of log-corrected least significant bits.
Claim 12
Dependent Claim
159 words
The encoding apparatus as defined in claim 1 further including means for decoding said m+l bit output samples in the log domain to produce reconstructed samples representative of the antilogarithms of said output samples in the non-log domain; said decoding means comprising: (A) means for tagging a logical one to said l least significant bits of said m+l bit output samples to produce at an output thereof a fifth set of binary numbers having a logical one in the highest significant bit position thereof: (B) means responsive to said m most significant bits of said m+l bit output samples for determining a value representing the number of shifts toward the position of lesser significance of said fifth set of binary numbers necessary to define said reconstructed samples; and (C) means, coupled to said value determining means, for shifting said fifth set of binary numbers toward said position of lesser significance to produce said reconstructed samples in the non-log domain.
Claim 13
Dependent Claim
73 words
The encoding/decoding apparatus as defined in claim 11 wherein said value determining means comprises: (A) means for subtracting said fixed binary value from said m most significant bits of said m+l bit output samples; and (B) means for selectively inverting the output value of said subtracting means to generate said value representing the number of shifts of said fifth set of binary numbers required to form said reconstructed samples in the non-log domain.
Claim 14
Dependent Claim
33 words
The encoding/decoding apparatus as defined in claim 12 wherein said subtracting means comprises means for additng 2's complement of said fixed binary value to the m most significant bits of said output samples.
Claim 15
Dependent Claim
62 words
The encoding/decoding apparatus as defined in claim 12 wherein said selectively inverting means comprises a plurality of NAND gates, each (a) having as a first input the inverted value of the most significant bit of said output of said subtracting means, and (b) having as a second input the respective one of the remaining bits of said output of said subtracting means.
Claim 16
Dependent Claim
62 words
The encoding/decoding apparatus as defined in claim 11 wherein said value determining means comprises a plurality of NAND gages, each (a) having as a first input the highest significance bit of said m most significant bits of said m+l bit output samples, and (b) having as a second input the respective one of the remaining bits of said m most significant bits.
Claim 17
Dependent Claim
32 words
The encoding/decoding apparatus as defined in claim 11 wherein said value determining means comprises means for inverting the m-1 least significant bits of the m most significant bits of said output samples.
Claim 18
Dependent Claim
207 words
The encoding apparatus as defined in claim 1 further including means for decoding said m+l bit output samples in the log domain to produce reconstructed samples representative of the antilogarithms of said output samples in the non-log domain; said decoding means comprising: (A) truncation fixup means responsive to said m most significant bits of said m+l bit output samples for adding correction factors to said output samples to produce a sixth set of binary numbers such that said reconstructed samples are rounded off to the nearest integer; (B) means, coupled to said truncation fixup means, for tagging a logical one the l least significant bits of said sixth set of binary numbers to produce a seventh set of binary numbers having a logical one in the highest significant bit position thereof; (C) means responsive to the m most significant bits of said sixth set of binary numbers for determining a value representing the number of shifts toward the position of lesser significance of said seventh set of binary numbers necessary to form said reconstructed samples; and (D) means, coupled to said value determining means, for shifting said seventh set of binary numbers toward said position of lesser significance to produce said reconstructed samples in the non-log domain.
Claim 19
Dependent Claim
72 words
The encoding/decoding apparatus as defined inclaim 17 wherein said truncation fixup means comprises a ROM to which said m most significant bits of said output samples are applied as address codes, and which is programmed to contain the associated correction factors at the respective memory locations; wherein said truncation fixup means further includes means for combining said correction factors with said output samples to generate said sixth set of truncation-corrected binary numbers.
Claim 20
Dependent Claim
258 words
The encoding apparatus as defined in claim 8 further including means for decoding said m+l bit log-corrected output samples in the log domain to produce reconstructed samples representative of the antilogarithms of said output samples in the non-log domain; said decoding means comprising: (A) antilog fixup means responsive to said l least significant bits of said m+l bit log-corrected output samples for modifying said l least significant bits thereof to adjust for the differences between said log-linear approximation and said logarithmic function to produce an eights set of binary log-linear output values; (B) truncation fixup means responsive to the m most significant bits of said eights set of log-linear output values for adding respective correction factors thereto to produce a ninth set of binary numbers such that said reconstructed samples are rounded off to the nearest integer; (C) means, coupled to said truncation fixup means, for tagging a logical one to the l least significant bits of said ninth set of binary numbers to produce a tenth set of binary numbers having a logical one in the highest significant bit position thereof; (D) means responsive to the m most significant bits of said ninth set of binary numbers for determining a value representing the number of shifts toward the position of lesser significance of said tenth set of binary numbers necessary to form said reconstructed samples; and (E) means, coupled to said value determining means, for shifting said tenth set of binary numbers toward said position of lesser significance to produce said reconstructed samples in the non-log domain.
Claim 21
Dependent Claim
94 words
The encoding/decoding apparatus as defined in claim 19 wherein said antilog fixup means includes a ROM to which said l least significant bits of said log-corrected output samples are fed as address codes, and which is programmed to contain the log-linear values thereof at the respective memory locations; said antilog fixup means further having means for merging said m most significant bits of said log-corrected output samples with said log-linear values of said l least significant bits at the output of said antilog fixup ROM to generate said eight set of log-linear output values.
Claim 22
Dependent Claim
249 words
A digital signal processing apparatus for encoding n-bit binary input samples to produce m+l bit binary output samples representative of a given logarithmic function of said input samples; each of said binary input samples being represented by n binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said binary output samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; said encoding apparatus comprising: (A) an input terminal for applying said n-bit binary input samples; (B) means, coupled to said input terminal, for determining a number r corresponding to the bit position of highest significance exhibiting a logical one state in the respective one of said input samples, and generating an equivalent binary value at an output thereof; (C) selectively-actuated means, coupled to said bit position determining, for adding a predetermined value to said equivalent binary values for non-zero input samples to generate m-bit binary values representing the m most significant bits of said output samples; (D) means, coupled to said input terminal, for generating the l-bit binary products of the n-r least significant bits of said input samples times 2r; and (E) means for concatenating said m-bit binary values with said l-bit binary products as the most and least significant bits respectively of said output samples.
Claim 23
Dependent Claim
249 words
A digital signal processing apparatus for encoding n-bit binary input samples to produce m+l bit binary output samples representative of a given logarithmic function of said input samples; each of said binary input samples being represented by n binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said binary output samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; said encoding apparatus comprising: (A) an input terminal for applying said n-bit binary input samples; (B) means, coupled to said input terminal, for determining a number r corresponding to the bit position of highest significance exhibiting a logical one state in the respective one of said input samples, and generating an equivalent binary value at an output thereof; (C) selectively-actuated means, coupled to said bit position determining, for adding a predetermined value to said equivalent binary values for non-zero input samples to generate m-bit binary values representing the m most significant bits of said output samples; (D) means, coupled to said input terminal, for generating the l-bit binary products of the n-r least significant bits of said input samples times 2r; and (E) means for concatenating said m-bit binary values with said l-bit binary products as the most and least significant bits respectively of said output samples.
Claim 24
Dependent Claim
79 words
The encoding apparatus as defined in claim 21 wherein said equivalent binary value at said output of said bit position determining means varies from 1 to n as said highest significance bit exhibiting a logical one state in said input samples shifts from said least signifcant bit position position to said most significant bit position position respectively; wherein said output of said bit position determining means is zero in the absence of a logical one in said input samples.
Claim 25
Dependent Claim
275 words
A digital signal processing apparatus for decoding m+l bit binary samples in the log domain to produce reconstructed binary samples representative of the antilogarithms of said log samples; said binary log samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; the m most significant bits of said m+l bit binary log samples representing the bit position of highest significance exhibiting a logical one state in said reconstructed samples in the non-log domain; said decoding apparatus comprising: (A) truncation fixup means responsive to said m most significant bits of said m+l bit binary log samples for adding correction factors to said binary log samples to produce a first set of binary numbers such that said reconstructed samples are rounded off to the nearest integer; (B) means, coupled to said truncation fixup means, for tagging a logical one to the l least significant bits of said first set of binary numbers to produce a second set of binary numbers having a logical one in the highest significant bit position thereof; (C) means responsive to the m most significant bits of said second set of binary numbers for determining a value representing the number of shifts toward the position of lesser significance of said second set of binary numbers necessary to form said reconstructed samples; and (D) means, coupled to said value determining means, for shifting said second set of binary numbers toward said position of lesser significance to produce said reconstructed samples in the non-log domain.
Claim 26
Dependent Claim
275 words
A digital signal processing apparatus for decoding m+l bit binary samples in the log domain to produce reconstructed binary samples representative of the antilogarithms of said log samples; said binary log samples being represented by m+l binary bits arranged in order of significance from a least significant bit position to a most significant bit position; each of said bits exhibiting first and second states representing logical one's and logical zero's respectively; the m most significant bits of said m+l bit binary log samples representing the bit position of highest significance exhibiting a logical one state in said reconstructed samples in the non-log domain; said decoding apparatus comprising: (A) truncation fixup means responsive to said m most significant bits of said m+l bit binary log samples for adding correction factors to said binary log samples to produce a first set of binary numbers such that said reconstructed samples are rounded off to the nearest integer; (B) means, coupled to said truncation fixup means, for tagging a logical one to the l least significant bits of said first set of binary numbers to produce a second set of binary numbers having a logical one in the highest significant bit position thereof; (C) means responsive to the m most significant bits of said second set of binary numbers for determining a value representing the number of shifts toward the position of lesser significance of said second set of binary numbers necessary to form said reconstructed samples; and (D) means, coupled to said value determining means, for shifting said second set of binary numbers toward said position of lesser significance to produce said reconstructed samples in the non-log domain.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-09-29 | 1990-03-31 | 1990-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-29 | 1994-03-31 | 1994-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-29 | 1998-03-31 | 1998-09-30 | $7700.00 | Window Closed / Lapsed |