Patent US4613381A successfully refreshed from Google Patents.
US4613381A
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Method for fabricating a thyristor
Assignee: Toshiba Corp
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Filing: 1984-08-27
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Granted: 1986-09-23
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Expires: 2004-08-27
Abstract
Abstract In a method for fabricating a thyristor in which n-type impurities are diffused in a p-base of a pnp wafer to form an n + -emitter, the step of diffusing the n-type impurities for forming the n + -emitter has the conditions which are set not to exceed the range where the amount of doped impurities is smaller than that which is electrically activated, thereby performing the gettering process by diffusing n-type impurities in two surfaces of the pnpn wafer in which the n + -emitter having no defects is formed. Even if a thyristor obtained by the above processes has a high off-state voltage, it has a low on-state voltage, a short turn-off time and a small variation in a reverse recovery charge.
Inventors
- 👤 Tsuneo Ogura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:24
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1404; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
115 words
A method for fabricating a thyristor comprising the steps of: (a) diffusing p-type impurities in two surfaces of an n-type silicon substrate to form a p-emitter and a p-base; (b) selectively diffusing n-type impurities in a surface of said p-base of a pnp wafer having said emitter and said p-base so as to form an n + -emitter having a surface impurity concentration not exceeding 10 20 /cm 3 ; (c) performing a gettering process by diffusing n-type impurities to a small depth in two surfaces of a pnpn wafer having said n + -emitter; and (d) diffusing a heavy metal to control a carrier lifetime in the pnpn wafer subjected to said gettering process.
Claim 2
Independent Claim
115 words
A method for fabricating a thyristor comprising the steps of: (a) diffusing p-type impurities in two surfaces of an n-type silicon substrate to form a p-emitter and a p-base; (b) selectively diffusing n-type impurities in a surface of said p-base of a pnp wafer having said emitter and said p-base so as to form an n + -emitter having a surface impurity concentration not exceeding 10 20 /cm 3 ; (c) performing a gettering process by diffusing n-type impurities to a small depth in two surfaces of a pnpn wafer having said n + -emitter; and (d) diffusing a heavy metal to control a carrier lifetime in the pnpn wafer subjected to said gettering process.
Claim 3
Dependent Claim
97 words
A method according to claim 1, wherein the step (b) for forming said n + -emitter by diffusing the n-type impurities comprises depositing the n-type impurities on the pnp wafer by keeping a temperature of a diffusion source at 5° C. or less and flow rates of an O 2 gas and an N 2 gas which carries said diffusion source are set at 1/20 or less of that of a main N 2 gas which carries said diffusion source, said N 2 gas and said O 2 gas; and thereafter driving in (slumping) the n-type impurities.
Claim 4
Dependent Claim
67 words
A method according to claim 1, wherein the step (c) for diffusing the n-type impurities for said gettering process is performed in the state wherein a mask for forming said n + -emitter is left at the cathode side, thereby obtaining said n + -emitter having a plurality of defects from the surface thereof to a depth of several micrometers and having few defects below several micrometers.
Claim 5
Independent Claim
139 words
A method for fabricating a thyristor comprising the steps of: (a) diffusing p-type impurities in two surfaces of an n-type silicon substrate to form a p-emitter and a p-base; (b) selectively diffusing n-type impurities in a surface of a p-base of a pnp wafer having said p-emitter and said p-base to form an n + -emitter so as not to exceed a surface impurity concentration of 10 20 /cm 3 ; (c) performing a gettering process by diffusing n-type impurities in two surfaces of a pnpn wafer having said n + -emitter; (d) annealing the pnpn wafer subjected to the gettering process in an inert gas at a temperature of 600° to 1,000° C. for up to 10 hours; and (e) diffusing a heavy metal to control a carrier lifetime in the pnpn wafer subjected to said gettering process.
Claim 6
Independent Claim
139 words
A method for fabricating a thyristor comprising the steps of: (a) diffusing p-type impurities in two surfaces of an n-type silicon substrate to form a p-emitter and a p-base; (b) selectively diffusing n-type impurities in a surface of a p-base of a pnp wafer having said p-emitter and said p-base to form an n + -emitter so as not to exceed a surface impurity concentration of 10 20 /cm 3 ; (c) performing a gettering process by diffusing n-type impurities in two surfaces of a pnpn wafer having said n + -emitter; (d) annealing the pnpn wafer subjected to the gettering process in an inert gas at a temperature of 600° to 1,000° C. for up to 10 hours; and (e) diffusing a heavy metal to control a carrier lifetime in the pnpn wafer subjected to said gettering process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-22 | 1990-03-24 | 1990-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-22 | 1994-03-24 | 1994-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-22 | 1998-03-24 | 1998-09-23 | $7700.00 | Window Closed / Lapsed |