Integrated circuit device having a circuit means for detecting a disconnection of input signal line

Claim 2

A semiconductor integrated circuit including a circuit for detecting disconnection of a signal line from an input terminal, said detecting circuit comprising: first and second power terminals, a power voltage being supplied between said first and second power terminals; an emitter follower transistor (Q10) having a base d.c. coupled to said input terminal, a collector d.c. coupled to said first power terminal and an emitter said emitter follower transistor transferring a signal at said input terminal to its emitter; a load transistor (Q11) for said emitter follower transistor having a collector d.c. coupled to the emitter of said emitter follower transistor, an emitter d.c. coupled to said second power terminal and a base; a means (R7) for supplying a base current for said load transistor, said supplying means being inserted between said first power terminal and the base of said load transistor; and a detection output circuit powered by said power voltage and having an input port receiving the potential at the base of said load transistor, and an output port producing a first output potential when said signal line is connected to said input terminal and a second output potential different from said first output potential when said signal line is not connected to said input terminal.

Claim 3

A semiconductor integrated circuit as claimed in claim 1, wherein said detection output circuit includes means for producing said second output potential in response to an increase in a base current of said lead transistor which is caused by the cut-off state of said emitter follower transistor when the base of said emitter follower transistor is disconnected from said signal line.

Claim 4

A semiconductor integrated circuit as claimed in claim 2, wherein said detection output circuit comprises a third transistor (Q12) having a base connected to said input port, a collector d.c. coupled to said first power terminal and an emitter, a fourth transistor (Q13) having a base connected to the emitter of said third transistor, an emitter d.c. coupled to said second power terminal and a collector connected to said output port and a load resistor (R10) inserted between said output port and said first power terminal.

Claim 5

A semiconductor integrated circuit as claimed in claim 1, wherein said detecting circuit further comprises another input terminal, another emitter follower transistor having a base coupled to said another input terminal, and another load transistor for said another emitter follower transistor, an emitter of said another emitter follower transistor being coupled to the collector of said another load transistor, the base of said another load transistor being coupled to said supply means.

Claim 6

A semiconductor integrated circuit as claimed in claim 3, wherein said detecting circuit further comprises another input terminal, another emitter follower transistor, and another load transistor, said another input terminal being coupled to the base of the said another emitter follower transistor, the emitter of said another emitter follower transistor being coupled to the collector of said another load transistor, the base of said another load transistor being coupled to said supplying means.

Claim 7

A semiconductor integrated circuit including a circuit for detecting disconnection of a signal line from an input terminal, said detecting circuit comprising: an input terminal (13) connected to said signal line (32) for receiving an input signal; first and second power terminals, a power voltage being supplied between said first and second power terminals; a first transistor (Q10) having a base connected to said input terminal, a collector connected to said first power terminal and an emitter; a second transistor (Q11) having a collector connected to the emitter of said first transistor, an emitter coupled to said second power terminal through a first resistor (R6) and a base, said first transistor operating as an emitter follower with a load of said second transistor and said first resistor; a second resistor (R7) inserted between said first power terminal and the base of said second transistor; a third transistor (Q12) having a base connected to the base of said second transistor, a collector coupled to said first power terminal and an emitter connected to said second power terminal through a third resistor (R8); a fourth transistor (Q13) having a base connected to the emitter of said third transistor, a collector connected to said first power terminal through a fourth resistor (R10) and an emitter connected to said second power terminal through a fifth resistor (R9); and a detection terminal (19) connected to the collector of said fourth transistor, whereby a large part of the current flowing through said second resistor is supplied to said base of said third transistor when said input terminal is connected to said signal line, and a large part of the current flowing through said second resistor flows into the base of said second transistor, when said input terminal is under an open condition and said first transistor turns off.

Claim 8

A semiconductor integrated circuit including a circuit for detecting disconnection of a signal line from an input terminal, said detecting circuit comprising: an input terminal (13) connected to said signal line (32) for receiving an input signal; first and second power terminals, a power voltage being supplied between said first and second power terminals; a first transistor (Q10) having a base connected to said input terminal, a collector connected to said first power terminal and an emitter; a second transistor (Q11) having a collector connected to the emitter of said first transistor, an emitter coupled to said second power terminal through a first resistor (R6) and a base, said first transistor operating as an emitter follower with a load of said second transistor and said first resistor; a second resistor (R7) inserted between said first power terminal and the base of said second transistor; a third transistor (Q12) having a base connected to the base of said second transistor, a collector coupled to said first power terminal and an emitter connected to said second power terminal through a third resistor (R8); a fourth transistor (Q13) having a base connected to the emitter of said third transistor, a collector connected to said first power terminal through a fourth resistor (R10) and an emitter connected to said second power terminal through a fifth resistor (R9); and a detection terminal (19) connected to the collector of said fourth transistor, whereby a large part of the current flowing through said second resistor is supplied to said base of said third transistor when said input terminal is connected to said signal line, and a large part of the current flowing through said second resistor flows into the base of said second transistor, when said input terminal is under an open condition and said first transistor turns off.

Claim 9

An integrated circuit device having a plurality of input terminals, each to be connected to a respective signal line for receiving a respective input signal and including a circuit for detecting disconnections of signal lines from corresponding input terminals, said detecting circuit comprising: first and second power terminals, a power voltage being supplied between said first and second power terminals; a plurality of emitter follower transistors (Q10), each having a base d.c. coupled to one of said input terminals, a collector d.c. coupled to said first power terminal and an emitter, each of said emitter follower transistor transferring an input signal at its corresponding input terminal to the emitter thereof; a plurality of lead transistors (Q11) for said emitter follower transistor, each having a collector d.c. coupled to said second power terminal and a base; a means (R7) for supplying base currents to said load transistors, said supplying means being inserted between said first power terminal and the bases of said load transistors; and a detection output circuit powered by said power voltage and having an input port receiving the potentials at the bases of said load transistors, and an output port producing a first output potential when all of said signal lines are connected to their corresponding input terminals and a second output potential different from said first output potential when at least one of said signal lines is not connected to its corresponding input terminal.

Claim 10

An integrated circuit device having a plurality of input terminals, each to be connected to a respective signal line for receiving a respective input signal and including a circuit for detecting disconnections of signal lines from corresponding input terminals, said detecting circuit comprising: first and second power terminals, a power voltage being supplied between said first and second power terminals; a plurality of emitter follower transistors (Q10), each having a base d.c. coupled to one of said input terminals, a collector d.c. coupled to said first power terminal and an emitter, each of said emitter follower transistor transferring an input signal at its corresponding input terminal to the emitter thereof; a plurality of lead transistors (Q11) for said emitter follower transistor, each having a collector d.c. coupled to said second power terminal and a base; a means (R7) for supplying base currents to said load transistors, said supplying means being inserted between said first power terminal and the bases of said load transistors; and a detection output circuit powered by said power voltage and having an input port receiving the potentials at the bases of said load transistors, and an output port producing a first output potential when all of said signal lines are connected to their corresponding input terminals and a second output potential different from said first output potential when at least one of said signal lines is not connected to its corresponding input terminal.

Claim 11

An integrated circuit as claimed in claim 7, wherein said detection output circuit includes means for producing said second output potential in response to an abnormally large flow of base current to at least one of second transistors.

Claim 12

An integrated circuit as claimed in claim 8, wherein said detection output circuit includes a third transistor (Q12) having a base connected to said input port, a collector d.c. coupled to said first power terminal and an emitter, a fourth transistor (Q13) having a base connected to the emitter of said third transistor, an emitter d.c. coupled to said second power terminal and a collector connected to said output port and a load resistor (R10) inserted between said output port and said first power terminal.