US3582665A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latching threshold detector
Assignee: United States Department of the Navy
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Filing: 1968-08-16
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Granted: 1971-06-01
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Expires: 1988-08-16
Abstract
Abstract A trigger circuit for providing an output signal in response to an input signal only when said input signal meets a predetermined set of requirements. An input signal is fed, in parallel, to two class A emitter followers. Each emitter follower is associated with a respective dual-transistor circuit, one circuit effecting the positive trigger level and the other effecting the negative trigger level. The trigger levels depend solely on the emitterto-base voltage required to turn on the controlling transistors and therefore the trigger levels are independent of variations in the supply voltage. In one embodiment, the instant circuit serves as a zero-crossing detector; and in another embodiment it serves as a general amplitude detecting circuit.
Inventors
- 👤 Edward F Prozeller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:13
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
428 words
A latching threshold detector adapted to be connected to a source of periodically varying input voltage signal and comprising: an output terminal at which appears an output signal which is latched to a first voltage level when said input voltage signal is of a first predetermined threshold level and which is latched to a second voltage level at such time as said incoming signal is of a second predetermined threshold level; a source of supply voltage; a first semiconductor device comprising: a control electrode connected to receive said input voltage signal, and a pair of primary current-conducting electrodes, one of said primary electrodes being connected to said output terminal and to said supply voltage source and the other of said primary electrodes being connected to ground, the signal appearing at said output terminal being at said first voltage level when said first semiconductor device is in its conductive state; a second semiconductor device whose conduction state is determined by and corresponds to the conduction state of said first semiconductor device and comprising: a control electrode connected to one of said primary current conducting electrodes of said first semiconductor device, and a pair of primary current-conducting electrodes, one of said primary electrodes being connected in a feedback path to said control electrode of said first semiconductor device, said feedback path maintaining said first semiconductor device in its conductive state, thereby causing said output signal to be latched to said first voltage level, the other of said primary electrodes being connected to said supply voltage; a third semiconductor device of opposite conductivity type as said first semiconductor device and comprising: a pair of primary conducting electrodes, one of said primary electrodes being connected to ground, and a control electrode connected to receive said input voltage signal, a fourth semiconductor device whose conduction state is determined by and corresponds to the conduction state of said third semiconductor device, and comprising: a control electrode connected to the other of said primary conducting electrodes of said third semiconductor device and, a pair of primary current-conducting electrodes, one of said primary electrodes being connected to said feedback path for destroying the ability of said feedback path to maintain said first semiconductor device in its conductive state when said fourth semiconductor device is in its conductive state thereby causing said output signal to be latched to said second voltage level, and the other of said primary electrodes being connected to said supply voltage; the signal appearing at said output terminal being at said second voltage level when third semiconductor device is in its conductive state.
Claim 2
Dependent Claim
428 words
A latching threshold detector adapted to be connected to a source of periodically varying input voltage signal and comprising: an output terminal at which appears an output signal which is latched to a first voltage level when said input voltage signal is of a first predetermined threshold level and which is latched to a second voltage level at such time as said incoming signal is of a second predetermined threshold level; a source of supply voltage; a first semiconductor device comprising: a control electrode connected to receive said input voltage signal, and a pair of primary current-conducting electrodes, one of said primary electrodes being connected to said output terminal and to said supply voltage source and the other of said primary electrodes being connected to ground, the signal appearing at said output terminal being at said first voltage level when said first semiconductor device is in its conductive state; a second semiconductor device whose conduction state is determined by and corresponds to the conduction state of said first semiconductor device and comprising: a control electrode connected to one of said primary current conducting electrodes of said first semiconductor device, and a pair of primary current-conducting electrodes, one of said primary electrodes being connected in a feedback path to said control electrode of said first semiconductor device, said feedback path maintaining said first semiconductor device in its conductive state, thereby causing said output signal to be latched to said first voltage level, the other of said primary electrodes being connected to said supply voltage; a third semiconductor device of opposite conductivity type as said first semiconductor device and comprising: a pair of primary conducting electrodes, one of said primary electrodes being connected to ground, and a control electrode connected to receive said input voltage signal, a fourth semiconductor device whose conduction state is determined by and corresponds to the conduction state of said third semiconductor device, and comprising: a control electrode connected to the other of said primary conducting electrodes of said third semiconductor device and, a pair of primary current-conducting electrodes, one of said primary electrodes being connected to said feedback path for destroying the ability of said feedback path to maintain said first semiconductor device in its conductive state when said fourth semiconductor device is in its conductive state thereby causing said output signal to be latched to said second voltage level, and the other of said primary electrodes being connected to said supply voltage; the signal appearing at said output terminal being at said second voltage level when third semiconductor device is in its conductive state.
Claim 3
Dependent Claim
39 words
A latching threshold detector as claimed in claim 1 wherein said semiconductor devices are transistors, said control electrodes of said semiconductor devices are bases, and said pair of primary current-conducting electrodes of said semiconductor devices are emitters and collectors.
Claim 4
Dependent Claim
62 words
The trigger circuit of claim 2 and further comprising first emitter follower transistor means for receiving said incoming signal and for transmitting to said first transistor means a signal in response to said incoming sIgnal; and second emitter follower transistor means for receiving said incoming signal and for transmitting to said third transistor means a signal in response to said incoming signal.
Claim 5
Dependent Claim
47 words
The circuit of claim 3 and further comprising first biasing means associated with said first transistor means for setting the upper trigger level of the trigger circuit; and second biasing means associated with said third transistor means for setting the lower trigger level of the trigger circuit.
Claim 6
Dependent Claim
385 words
A trigger circuit for receiving an incoming signal and for issuing an output signal in response thereto, the output signal being of such a nature that it indicates whether the input signal meets a predetermined amplitude requirement, and comprising an input terminal for receiving an incoming signal; an output terminal for issuing a signal having either a first or a second voltage level; a source of positive and negative control voltage; a first transistor having a collector, an emitter and a base, the base being connected to said input terminal, and the collector forming said output terminal; the emitter being connected to ground; a second transistor of opposite conductivity type from said first transistor having a collector, an emitter and a base, said base of said second transistor being connected to said collector of said first transistor thereby causing said first transistor to control the conduction state of said second transistor, said first and said second transistors always being in the same conduction state, said emitter being connected to said source of positive control voltage and said collector of said second transistor being connected to both said input terminal and to said base of said first transistor, said collector-base connection causing a feedback path to be provided between said second and said first transistors, said second transistor having the capability of latching said first transistor in its conductive state; a third transistor of opposite conductivity type from said first transistor and in the conduction state opposite from that experienced by said first transistor, and having a collector, an emitter and a base, said base being connected to said input terminal, said emitter being connected to ground, and said collector being connected to said source of negative control a fourth transistor having a collector, an emitter and a base, said base of said fourth transistor being connected to said collector of said third transistor thereby causing said third transistor to control the conduction state of said fourth transistor, said third and said fourth transistors always being in the same conduction state, said collector being connected to said feedback path destroying the ability of said feedback path to maintain said first semiconductor device in its conductive state when said fourth transistor is in its conductive state, said emitter being connected to said source of negative control voltage.
Claim 7
Dependent Claim
385 words
A trigger circuit for receiving an incoming signal and for issuing an output signal in response thereto, the output signal being of such a nature that it indicates whether the input signal meets a predetermined amplitude requirement, and comprising an input terminal for receiving an incoming signal; an output terminal for issuing a signal having either a first or a second voltage level; a source of positive and negative control voltage; a first transistor having a collector, an emitter and a base, the base being connected to said input terminal, and the collector forming said output terminal; the emitter being connected to ground; a second transistor of opposite conductivity type from said first transistor having a collector, an emitter and a base, said base of said second transistor being connected to said collector of said first transistor thereby causing said first transistor to control the conduction state of said second transistor, said first and said second transistors always being in the same conduction state, said emitter being connected to said source of positive control voltage and said collector of said second transistor being connected to both said input terminal and to said base of said first transistor, said collector-base connection causing a feedback path to be provided between said second and said first transistors, said second transistor having the capability of latching said first transistor in its conductive state; a third transistor of opposite conductivity type from said first transistor and in the conduction state opposite from that experienced by said first transistor, and having a collector, an emitter and a base, said base being connected to said input terminal, said emitter being connected to ground, and said collector being connected to said source of negative control a fourth transistor having a collector, an emitter and a base, said base of said fourth transistor being connected to said collector of said third transistor thereby causing said third transistor to control the conduction state of said fourth transistor, said third and said fourth transistors always being in the same conduction state, said collector being connected to said feedback path destroying the ability of said feedback path to maintain said first semiconductor device in its conductive state when said fourth transistor is in its conductive state, said emitter being connected to said source of negative control voltage.
Claim 8
Dependent Claim
52 words
The trigger circuit as claimed in claim 5 and further comprising first biasing means connected to the emitter of said first transistor for determining the upper trigger level of the circuit; and second biasing means connected to the emitter of said third transistor for determining the lower trigger level of the circuit.
Claim 9
Dependent Claim
62 words
The circuit of claim 6 wherein the collector of said fourth transistor is connected to the base of said first transistor and the collector of said second transistor in such a manner that when said fourth transistor is in its conductive state, current is not allowed to flow from the collector of said second transistor into the base of said first transistor.
Claim 10
Dependent Claim
58 words
The trigger circuit of claim 7 and further comprising first emitter follower means for receiving said incoming signal and for transmitting to said first transistor a signal in response to said incoming signal; and second emitter follower means for reCeiving said incoming signal and for transmitting to said third transistor a signal in response to said incoming signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |