Patent US4611237A successfully refreshed from Google Patents.
US4611237A
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Toshiba Corp
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Filing: 1984-07-30
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Granted: 1986-09-09
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Expires: 2004-07-30
Abstract
Abstract A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.
Inventors
- 👤 Kazunori Ohuchi
- 👤 Mitsugi Ogura
- 👤 Kenji Natori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:30
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10W20/20
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
192 words
A seminconductor integrated circuit comprising: source and drain regions of a MOS transistor provided in a semiconductor substrate; a first insulation layer serving as a gate insulation layer and provided on the channel region between said source and drain regions; a gate electrode provided on said first insulation layer; a second insulation layer covering said source and drain regions and said gate electrode; first and second conductive layers provided on said second insulation layer and contacting respective surfaces of said source and drain regions through respective contact holes formed through said second insulation layer; a third insulation layer covering the main surface portion of said MOS transistor; a source takeout electrode which contacts one end of said source region and extends over said third insulation layer, and which is separated from said first conductive layer provided on said source region; a drain takeout electrode which contacts one end of said drain region and extends over said third insulation layer, and which is separated from said second conductive layer provided on said drain region; and at least one interconnection layer provided on said third insulation layer and crossing said source and drain regions.
Claim 2
Dependent Claim
192 words
A seminconductor integrated circuit comprising: source and drain regions of a MOS transistor provided in a semiconductor substrate; a first insulation layer serving as a gate insulation layer and provided on the channel region between said source and drain regions; a gate electrode provided on said first insulation layer; a second insulation layer covering said source and drain regions and said gate electrode; first and second conductive layers provided on said second insulation layer and contacting respective surfaces of said source and drain regions through respective contact holes formed through said second insulation layer; a third insulation layer covering the main surface portion of said MOS transistor; a source takeout electrode which contacts one end of said source region and extends over said third insulation layer, and which is separated from said first conductive layer provided on said source region; a drain takeout electrode which contacts one end of said drain region and extends over said third insulation layer, and which is separated from said second conductive layer provided on said drain region; and at least one interconnection layer provided on said third insulation layer and crossing said source and drain regions.
Claim 3
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 1, wherein said first and second conductive layers, said source takeout electrode and said drain takeout electrode are made of aluminum.
Claim 4
Dependent Claim
47 words
A semiconductor integrated circuit device according to claim 1, wherein said source takeout electrode is extended over said third insulation layer so as to cross said drain region and said drain takeout electrode is extended over said third insulation layer so as to cross said source region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-08 | 1990-03-10 | 1990-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-08 | 1994-03-10 | 1994-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-08 | 1998-03-10 | 1998-09-09 | $7700.00 | Window Closed / Lapsed |