Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
295 words
A television receiver incorporating a processing section for processing television/stereo-dual sound signals, said sound signals having a first sound carrier (f T1 ) which is modulated by a first sound signal (NF1), and a second sound carrier (f T2 ) which is modulated both by a second sound signal (NF2) and also by a pilot signal (fp) which is, in turn, modulated by a stereo-dual sound identifying signal (f K1 , f K2 ), said processing section comprising means for demodulating said first and said second sound carriers, respectively, forming said first sound signal, and said second sound signal along with said modulated pilot signal, a phase-locked loop having a frequency-controlled oscillator and a phase discriminator for controlling said frequency-controlled oscillator, said phase discriminator comparing a signal derived from said frequency-controlled oscillator with a reference signal which, in regard to frequency and phase, is in a fixed relationship to the modulated pilot signal, and a synchronous demodulator, coupled to an output of said phase-locked loop, for demodulating said modulated pilot signal thereby recovering said stereo-dual sound identifying signal, characterized in that said processing section further comprises a mixer for receiving at least said modulated second sound carrier, to which is also applied an output signal of said frequency-controlled oscillator, said mixer converting said modulated second sound carrier to a lower frequency range, said demodulating means being coupled to an output of said mixer and comprising at least a demodulator for said modulated second sound carrier forming at an output thereof said second sound signal and said modulated pilot signal, and a filter coupled to the output of said demodulatoar for selecting the modulated pilot signal therefrom, said modulated pilot signal then being applied to said phase discriminator in said phase-locked loop as said reference signal.
Claim 2
Dependent Claim
295 words
A television receiver incorporating a processing section for processing television/stereo-dual sound signals, said sound signals having a first sound carrier (f T1 ) which is modulated by a first sound signal (NF1), and a second sound carrier (f T2 ) which is modulated both by a second sound signal (NF2) and also by a pilot signal (fp) which is, in turn, modulated by a stereo-dual sound identifying signal (f K1 , f K2 ), said processing section comprising means for demodulating said first and said second sound carriers, respectively, forming said first sound signal, and said second sound signal along with said modulated pilot signal, a phase-locked loop having a frequency-controlled oscillator and a phase discriminator for controlling said frequency-controlled oscillator, said phase discriminator comparing a signal derived from said frequency-controlled oscillator with a reference signal which, in regard to frequency and phase, is in a fixed relationship to the modulated pilot signal, and a synchronous demodulator, coupled to an output of said phase-locked loop, for demodulating said modulated pilot signal thereby recovering said stereo-dual sound identifying signal, characterized in that said processing section further comprises a mixer for receiving at least said modulated second sound carrier, to which is also applied an output signal of said frequency-controlled oscillator, said mixer converting said modulated second sound carrier to a lower frequency range, said demodulating means being coupled to an output of said mixer and comprising at least a demodulator for said modulated second sound carrier forming at an output thereof said second sound signal and said modulated pilot signal, and a filter coupled to the output of said demodulatoar for selecting the modulated pilot signal therefrom, said modulated pilot signal then being applied to said phase discriminator in said phase-locked loop as said reference signal.
Claim 3
Dependent Claim
60 words
A circuit arrangement as claimed in claim 1, characterized in that said phase-locked loop further comprises a frequency divider coupled to the output of the oscillator, said frequency divider having two outputs coupled, respectively, to said phase discriminator and to the synchronous demodulator, said two outputs providing signals having the same frequency and having a phase shift through 90° therebetween.
Claim 4
Dependent Claim
36 words
A circuit arrangement as claimed in claim 2, characterized in that the frequency divider divides the oscillator output signal by the ratio 1:n, where n is an integer between 108 and 120, preferably an even number.