US4610003A
Expired / Lapsed
US
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Dynamic type semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-08-31
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Granted: 1986-09-02
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Expires: 2004-08-31
Abstract
Abstract A dynamic type semiconductor memory device includes a memory cell having a capacitor for storing an amount of charge corresponding to data and, an n-channel MOS transistor to control charging and discharging to and from the capacitor, and a control unit to permit a read/write operation of the memory cell. The control unit of the memory device includes a drive circuit for generating turn on and turn off voltages, a charge pump circuit connected to the gate of the memory cell, and a switching element connected between the drive circuit and the gate of the MOS transistor.
Inventors
- 👤 Kenji Natori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/4085; G11C11/409
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
163 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turnoff votages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a large impedance element connected between said leak control means and the gate of said MOS transistor, a switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes said switching element nonconductive in response to the first turn off voltage with a delay time and conductive in response to the turn on voltage.
Claim 2
Dependent Claim
163 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turnoff votages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a large impedance element connected between said leak control means and the gate of said MOS transistor, a switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes said switching element nonconductive in response to the first turn off voltage with a delay time and conductive in response to the turn on voltage.
Claim 3
Dependent Claim
22 words
A dynamic type semiconductor memory device according to claim 1, wherein said large impedance element is a resistor having a large resistance.
Claim 4
Dependent Claim
20 words
A dynamic type semiconductor memory device according to claim 1, wherein said switching element is formed of a MOS transistor.
Claim 5
Dependent Claim
38 words
A dynamic type semiconductor memory device according to claim 1, wherein said drive means has a drive circuit which selectively generates either the turn on voltage or the first turn off voltage in accordance with a control signal.
Claim 6
Dependent Claim
18 words
A dynamic type semiconductor memory device according to claim 1, wherein said MOS transistor is on n-channel type.
Claim 7
Dependent Claim
50 words
A dynamic type semiconductor memory device according to claim 5, wherein said leak control means includes a pulse oscillator, and a charge pump circuit which generates the second turn off voltage in cooperation with said pulse oscillator, said second turn off voltage being lower than the first turn off voltage.
Claim 8
Dependent Claim
18 words
A dynamic type semiconductor memory device according to claim 1, wherein said MOS transistor is of p-channel type.
Claim 9
Dependent Claim
50 words
A dynamic type conductor memory device according to claim 7, wherein said leak control means includes a pulse oscillator, and a charge pump circuit which generates the second turn off voltage in cooperation with said pulse oscillator, said second turn off voltage being higher than the first turn off voltage.
Claim 10
Dependent Claim
177 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn of voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a first switching element connected between said leak control menas and the gate of said MOS transistor, a second switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes said first and second switching elements conductive and nonconductive in response to the first turn off voltage, respectively, and rendering said first and second switching elements nonconductive and conductive in response to the turn on voltage.
Claim 11
Dependent Claim
177 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn of voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a first switching element connected between said leak control menas and the gate of said MOS transistor, a second switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes said first and second switching elements conductive and nonconductive in response to the first turn off voltage, respectively, and rendering said first and second switching elements nonconductive and conductive in response to the turn on voltage.
Claim 12
Dependent Claim
20 words
A dynamic type semiconductor memory device according to claim 9, wherein said first and second switching elements are MOS transistors.
Claim 13
Dependent Claim
38 words
A dynamic type semiconductor memory device according to claim 9, wherein said drive means has a drive circuit which selectively generates either the turn on voltage or the first turn off voltage in accordance with a control signal.
Claim 14
Dependent Claim
18 words
A dynamic type semiconductor memory device according to claim 9, wherein said MOS transistor is of n-channel type.
Claim 15
Dependent Claim
50 words
A dynamic type semiconductor memory device according to claim 12, wherein said leak control means includes a pulse oscillator, and a charge pump circuit which generates the second turn off voltage in cooperation with said pulse oscillator, said second turn off voltage being lower than the first turn off voltage.
Claim 16
Dependent Claim
19 words
A dynamic type semiconductor memory device according to claim 9, wherein said first MOS transistor is of p-channel type,
Claim 17
Dependent Claim
50 words
A dynamic type semiconductor memory device according to claim 14, wherein said leak control means includes a pulse oscillator, and a charge pump circuit which generates the second turn off voltage in cooperation with said pulse oscillator, said second turn off voltage being higher than the first turn off voltage.
Claim 18
Dependent Claim
152 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a large impedance element connected between said leak control means and the gate of said MOS transistor, a switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which controls the conduction state of said switching element in accordance with an enable signal.
Claim 19
Dependent Claim
152 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a large impedance element connected between said leak control means and the gate of said MOS transistor, a switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which controls the conduction state of said switching element in accordance with an enable signal.
Claim 20
Dependent Claim
166 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a first switching element connected between said leak control means and the gate of said MOS transistor, a second switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes one of said first and second switching elements conductive and the other of said first and second switching elements nonconductive in response to an enable signal.
Claim 21
Dependent Claim
166 words
A dynamic type semiconductor memory device comprising: at least one memory cell including capacitive means for storing an amount of charge corresponding to data and a MOS transistor for controlling charging and discharging to and from said capacitive means; drive means for selectively generating turn on and first turn off voltages; leak control means for generating a second turn off voltage, an absolute value of a difference between the second turn off voltage and the turn on voltage being larger than that of a difference between the first turn off voltage and the turn on voltage; and voltage supplying means including a first switching element connected between said leak control means and the gate of said MOS transistor, a second switching element connected between said drive means and the gate of said MOS transistor, and a switching controller which makes one of said first and second switching elements conductive and the other of said first and second switching elements nonconductive in response to an enable signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |