Buffer circuit for semiconductor memory

Claim 2

A circuit for controlling a plurality of power transfer transistors, comprising: means responsive to a first enable signal for charging a node which is connected to control the state of said power transfer transistors; means responsive to a second enable signal for coupling said node to a reference voltage and for discharging said node to a predetermined voltage; means responsive to a first clock signal for isolating said node from said reference voltage; and means for coupling a negatively going clock signal to said node to drive said node to a voltage below said predetermined voltage whereby said power transfer transistors are rendered nonconductive.

Claim 3

A buffer circuit comprising: means for charging a first node; means for charging a second node; means responsive to a first signal for discharging said first and second nodes; means responsive to a second signal for isolating said first and second nodes; means for capacitively coupling a negative-going signal to said first and second nodes to lower the voltages on said nodes; and means for coupling said first and second nodes such that said second node is driven by said negative-going signal to a lower voltage than said first node.

Claim 4

A buffer circuit comprising: means for charging a first node; means for charging a second node; means responsive to a first signal for discharging said first and second nodes; means responsive to a second signal for isolating said first and second nodes; means for capacitively coupling a negative-going signal to said first and second nodes to lower the voltages on said nodes; and means for coupling said first and second nodes such that said second node is driven by said negative-going signal to a lower voltage than said first node.

Claim 5

A circuit for controlling a plurality of power transfer transistors, comprising: means responsive to a first enable signal for charging a first node, said first node connected to said power transfer transistor and a second node; means responsive to a second enable signal for discharging said first and said second nodes; means for coupling a negative-going clock signal to said first and second nodes to drive said first and second nodes to lower voltages; and means for coupling said first node to said second node such that said second node can be driven to a more negative voltage than said first node.

Claim 6

A circuit for controlling a plurality of power transfer transistors, comprising: means responsive to a first enable signal for charging a first node, said first node connected to said power transfer transistor and a second node; means responsive to a second enable signal for discharging said first and said second nodes; means for coupling a negative-going clock signal to said first and second nodes to drive said first and second nodes to lower voltages; and means for coupling said first node to said second node such that said second node can be driven to a more negative voltage than said first node.

Claim 7

The circuit recited in claim 3 including means for coupling said first node to a power node such that said first node is clamped such that it can be driven negative by no more than a predetermined voltage below a common voltage.

Claim 8

The circuit recited in claim 3 wherein said means for coupling said first node to said second node comprises a transistor having the drain terminal connected to a power node, the gate terminal coupled to said first node and the source terminal connected to said second node.

Claim 9

A circuit comprising: means responsive to an enable signal for charging a first node; means for charging a second node; means for charging a third node; means for charging a fourth node; means responsive to an inverse signal of said enable signal for discharging said first, second and third nodes; means responsive to a first clock signal for discharging said fourth node; means responsive to a second clock signal for negatively driving the voltage on said first node; means responsive to said second clock signal for negatively driving the voltage on said third node; and means for coupling said first node and said third node to permit said third node to be driven to a more negative voltage than said first node.

Claim 10

A circuit comprising: means responsive to an enable signal for charging a first node; means for charging a second node; means for charging a third node; means for charging a fourth node; means responsive to an inverse signal of said enable signal for discharging said first, second and third nodes; means responsive to a first clock signal for discharging said fourth node; means responsive to a second clock signal for negatively driving the voltage on said first node; means responsive to said second clock signal for negatively driving the voltage on said third node; and means for coupling said first node and said third node to permit said third node to be driven to a more negative voltage than said first node.

Claim 11

The circuit recited in claim 6 wherein said means for charging a first node comprises a transistor having the gate terminal thereof connected to receive said enable signal, the drain terminal thereof connected to a power node and the source terminal thereof connected to said first node.

Claim 12

The circuit recited in claim 6 wherein said means for charging a second node comprises: a Schmitt trigger circuit having the input thereof connected to said first node; a first transistor having the drain and source terminals connected between said first and second nodes and the gate terminal thereof connected to the output of said Schmitt trigger circuit; a second transistor having the gate terminal connected to the output of said Schmitt trigger circuit, the drain terminal connected to a fifth node and the source terminal connected to a common node; a capacitor connected between said second node and said fifth node; and a third transistor having the gate terminal connected to said second node, the drain terminal connected to a power node and the source terminal connected to said fifth node.

Claim 13

The circuit recited in claim 6 wherein said means for charging a third node comprises a transistor having the gate terminal connected to said second node, the drain terminal connected to a power node and the source terminal connected to said third node.

Claim 14

The circuit recited in claim 6 wherein said means for charging a fourth node comprises a transistor having the drain terminal connected to a power node, the source terminal connected to said fourth node, and the gate terminal connected to said third node.

Claim 15

The circuit recited in claim 6 wherein said means for discharging said first, second and third nodes comprises: a first transistor having the drain terminal connected to said first node and the gate terminal connected to receive said inverse signal; a second transistor having the drain terminal connected to said third node and the gate terminal connected to receive said inverse signal; a third transistor having the drain terminal connected to the source terminal of said first transistor the source terminal connected to a common node and the gate terminal connected to said fourth node; and a fourth transistor having the drain terminal connected to the source terminal of said second transistor the source terminal connected to said common node and the gate terminal connected to said fourth node.

Claim 16

The circuit recited in claim 6 wherein said means for discharging said fourth node comprises a transistor having the drain and source terminals connected between said third and fourth nodes and the gate terminal connected to receive said first clock signal.

Claim 17

The circuit recited in claim 6 wherein said means for negatively driving the voltage on said first node comprises a first capacitor having a first terminal connected to said first node and a second terminal connected to receive said second clock signal.

Claim 18

The circuit recited in claim 6 wherein said means for negatively driving said third node comprises a second capacitor having a first terminal connected to said third node and the second terminal connected to receive said second clock signal.

Claim 19

The circuit recited in claim 6 wherein said means for coupling comprises a transistor having the drain terminal connected to a power node, the source terminal connected to said third node and the gate terminal connected to said second node.

Claim 20

The circuit recited in claim 6 including a keeper circuit for each of said first and third nodes, said keeper circuits connected respectively to said corresponding nodes for pulling the nodes connected thereto to a high voltage state when the corresponding node is at a voltage above a predetermined threshold.

Claim 21

A circuit for controlling a plurality of power transfer transistors, comprising: a first transistor for charging a first node, said first transistor having the drain terminal connected to a power node, the gate terminal connected to receive a first enable signal, and the source terminal connected to a fist node; a second transistor for interconnecting said first node to a second node, said second transistor having the drain and source terminals connected between said first and second nodes; a Schmitt trigger inverter circuit having the input connected to said first node and the output connected to the gate terminal of said second transistor; a third transistor having the drain terminal connected to said power node and the gate terminal connected to said second node; a first capacitor having the terminals thereof connected between said second node and the source terminal of said third transistor; a fourth transistor having the drain terminal connected to the source terminal of said third transistor, the gate terminal connected to the gate terminal of said second transistor and the source terminal connected to a common node; a fifth transistor for coupling said second node to a third node, said fifth transistor having the drain terminal connected to said power node, the gate terminal connected to said second node and the source terminal connected to said third node; a sixth transistor having the drain terminal connected to said third node and the gate terminal connected to receive an inverse signal of said enable signal; a seventh transistor having the drain terminal connected to the source terminal of said sixth transistor, the gate terminal connected to a fourth node and the source terminal connected to said common node; an eighth transistor for charging said fourth node, said eighth transistor having the drain terminal connected to said power node, said gate terminal connected to said third node and the source terminal connected to said fourth node; a ninth transistor for connecting said third and fourth nodes, said ninth transistor having the drain terminal connected to said third node, the gate terminal connected to receive a first clock signal and the source terminal connected to said fourth node; a tenth transistor for discharging said first node, said tenth transistor having the drain terminal connected to said first node, the gate terminal connected to receive said inverse signal; an eleventh transistor having the drain terminal connected to the source terminal of said tenth transistor, the gate terminal connected to said fourth node and the source terminal connected to said common node; a second capacitor having a first terminal connected to said first node and a second terminal connected to receive a second clock signal which drives the voltage of said first node negatively when said second clock signal has a negative-going transition; a third capacitor having a first terminal connected to said third node and second terminal connected to receive said second clock signal which drives the voltage of said third node negatively when said second clock signal has a negative-going transition; a first keeper circuit connected to said first node for maintaining said first node at essentially the voltage of said power node when said first node has been driven to a voltage above a preset voltage; and a second keeper circuit connected to said third node for maintaining said third node at essentially the voltage of said power node when said third node has been driven to a voltage above a preset voltage.

Claim 22

A circuit for controlling a plurality of power transfer transistors, comprising: a first transistor for charging a first node, said first transistor having the drain terminal connected to a power node, the gate terminal connected to receive a first enable signal, and the source terminal connected to a fist node; a second transistor for interconnecting said first node to a second node, said second transistor having the drain and source terminals connected between said first and second nodes; a Schmitt trigger inverter circuit having the input connected to said first node and the output connected to the gate terminal of said second transistor; a third transistor having the drain terminal connected to said power node and the gate terminal connected to said second node; a first capacitor having the terminals thereof connected between said second node and the source terminal of said third transistor; a fourth transistor having the drain terminal connected to the source terminal of said third transistor, the gate terminal connected to the gate terminal of said second transistor and the source terminal connected to a common node; a fifth transistor for coupling said second node to a third node, said fifth transistor having the drain terminal connected to said power node, the gate terminal connected to said second node and the source terminal connected to said third node; a sixth transistor having the drain terminal connected to said third node and the gate terminal connected to receive an inverse signal of said enable signal; a seventh transistor having the drain terminal connected to the source terminal of said sixth transistor, the gate terminal connected to a fourth node and the source terminal connected to said common node; an eighth transistor for charging said fourth node, said eighth transistor having the drain terminal connected to said power node, said gate terminal connected to said third node and the source terminal connected to said fourth node; a ninth transistor for connecting said third and fourth nodes, said ninth transistor having the drain terminal connected to said third node, the gate terminal connected to receive a first clock signal and the source terminal connected to said fourth node; a tenth transistor for discharging said first node, said tenth transistor having the drain terminal connected to said first node, the gate terminal connected to receive said inverse signal; an eleventh transistor having the drain terminal connected to the source terminal of said tenth transistor, the gate terminal connected to said fourth node and the source terminal connected to said common node; a second capacitor having a first terminal connected to said first node and a second terminal connected to receive a second clock signal which drives the voltage of said first node negatively when said second clock signal has a negative-going transition; a third capacitor having a first terminal connected to said third node and second terminal connected to receive said second clock signal which drives the voltage of said third node negatively when said second clock signal has a negative-going transition; a first keeper circuit connected to said first node for maintaining said first node at essentially the voltage of said power node when said first node has been driven to a voltage above a preset voltage; and a second keeper circuit connected to said third node for maintaining said third node at essentially the voltage of said power node when said third node has been driven to a voltage above a preset voltage.

Claim 29

The method recited in claim 20 including the steps of: pulling said first node to the voltage of a power supply node when said first node is at a voltage above a predetermined voltage; and pulling said third node to the voltage of said power supply node when said third node is at a voltage above a predetermined voltage.