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US4609986A
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Programmable logic array device using EPROM technology
Assignee: Altera Corp
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Filing: 1984-06-14
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Granted: 1986-09-02
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Expires: 2004-06-14
Abstract
Abstract An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product terms" which are fed into another matrix comprised of "OR" gates, the outputs of which form sum-of-products expressions of the inputs to the AND arrays. Also contained in the macrocells are simple EPROM transistors which, when combined with other appropriate circuitry, form control elements, a plurality of storage registers (D flip-flops), feedback drivers, input drivers and output drivers, all integrated on the same substrate. The input drivers and feedback drivers provide input signals to the AND arrays and the outputs from the D flip-flops can be directed to either the feedback drivers or the output drivers. Control of data sources and destinations is determined by the control elements which in turn are determined by single EPROM transistors. Thus, the architecture as well as the logic function is programmable.
Inventors
- 👤 Robert F. Hartmann
- 👤 Yiu-Fai Chan
- 👤 Robert Frankovich
- 👤 Jung-Hsing Ou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712; H03K19/17716
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
251 words
A programmable integrated circuit logic array device, comprising: a plurality of input terminals for receiving input signals; a plurality of I/O terminals for receiving input signals and/or transmitting output signals; a first plurality of macrocells each including at least a first programmable AND array having a first plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, first sensing means connected to said first AND array, said first sensing means being responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding first data signal, first signal storage means, first feedback means, and first multiplexing means for selectively coupling said first data signal to one of said I/O terminals, to said first storage means, or to said first feedback means; and a plurality of data buses including a global input signal bus for coupling input signals from said input terminals to a first group of cells in the AND arrays of each said macrocell, a local feedback bus for coupling signals applied to the feedback means of at least some of said macrocells to a second group of cells of at least some of said macrocells, and a global feedback bus for coupling data signals applied to some of said feedback means to a third group of cells of all of said AND arrays of said macrocells.
Claim 2
Dependent Claim
251 words
A programmable integrated circuit logic array device, comprising: a plurality of input terminals for receiving input signals; a plurality of I/O terminals for receiving input signals and/or transmitting output signals; a first plurality of macrocells each including at least a first programmable AND array having a first plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, first sensing means connected to said first AND array, said first sensing means being responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding first data signal, first signal storage means, first feedback means, and first multiplexing means for selectively coupling said first data signal to one of said I/O terminals, to said first storage means, or to said first feedback means; and a plurality of data buses including a global input signal bus for coupling input signals from said input terminals to a first group of cells in the AND arrays of each said macrocell, a local feedback bus for coupling signals applied to the feedback means of at least some of said macrocells to a second group of cells of at least some of said macrocells, and a global feedback bus for coupling data signals applied to some of said feedback means to a third group of cells of all of said AND arrays of said macrocells.
Claim 3
Dependent Claim
117 words
A programmable integrated circuit logic array device as recited in claim 1 and further comprising: a second plurality of macrocells each including a programmable AND array having a plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, second sensing means responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding data signal, second signal storage means, second feedback terminal means, and second multiplexing means for coupling said second data signal to said second storage means or to said second feedback means.
Claim 4
Dependent Claim
63 words
A programmable integrated circuit logic array device as recited in claim 2 and further comprising: a third plurality of programmable AND arrays, various ones of which are shared by pairs of some of said first macrocells such that the sensing means of each macrocell sharing ones of said third arrays also detect the memory state of the cells of the shared AND arrays.
Claim 5
Dependent Claim
49 words
A programmable integrated circuit logic array device as recited in claim 3 and further comprising: a plurality of input latching circuits each coupling one of said input terminals to said input signal bus whereby input signals applied to said input terminals are maintained stable during certain intervals of time.
Claim 6
Dependent Claim
43 words
A programmable integrated circuit logic array device as recited in claim 4 wherein said input latching circuits include an input level shifting inverter stage, an output driver element, and a switchable pass gate and latch coupling the inverter stage to the driver element.
Claim 7
Dependent Claim
21 words
A programmable integrated circuit logic array device as recited in claim 5 wherein said memory cells are formed using EPROM technology.
Claim 8
Dependent Claim
50 words
A programmable integrated circuit logic array device as recited in claim 6 wherein each said sensing means includes at least one OR gate coupled to a plurality of the cells of a corresponding AND array, and each said AND array has a selectable number of product terms per OR gate.
Claim 9
Dependent Claim
47 words
A programmable integrated circuit logic array device as recited in claim 7 wherein each said multiplexing means includes a first switching means for connecting either the output of a corresponding sensing means or the output of a corresponding signal storage means to one of said I/O terminals.
Claim 10
Dependent Claim
44 words
A programmable integrated circuit logic array device as recited in claim 8 wherein each said multiplexing means further includes a second switching means operative to couple either the output of said corresponding sensing means or one of said I/O terminals to said feedback means.
Claim 11
Dependent Claim
21 words
A programmable integrated circuit logic array device as recited in claim 2 wherein said memory cells are formed using EPROM technology.
Claim 12
Dependent Claim
50 words
A programmable integrated circuit logic array device as recited in claim 2 wherein each said sensing means includes at least one OR gate coupled to a plurality of the cells of a corresponding AND array, and each said AND array has a selectable number of product terms per OR gate.
Claim 13
Dependent Claim
49 words
A programmable integrated circuit logic array device as recited in claim 1 and further comprising: a plurality of input latching circuits each coupling one of said input terminals to said input signal bus whereby input signals applied to said input terminals are maintained stable during certain intervals of time.
Claim 14
Dependent Claim
43 words
A programmable integrated circuit logic array device as recited in claim 12 wherein said input latching circuits include one input level shifting inverter stage, an output driver element, and a switchable pass gate and latch coupling the inverter stage to the driver element.
Claim 15
Dependent Claim
47 words
A programmable integrated circuit logic array device as recited in claim 1 wherein said first multiplexing means includes a first switching means for connecting either the output of said first sensing means or the output of said first signal storage means to one of said I/O terminals.
Claim 16
Dependent Claim
45 words
A programmable integrated circuit logic array device as recited in claim 14 wherein said first multiplexing means further includes a second switching means operative to couple either the output of said first sensing means or one of said I/O terminals to said first feedback means.
Claim 17
Dependent Claim
64 words
A programmable integrated circuit logic array device as recited in claim 1 and further comprising: a second plurality of programmable AND arrays, various ones of which are shared by pairs of some of said first macrocells such that the sensing means of each macrocell sharing ones of said second AND arrays also detect the memory state of the cells of the shared AND arrays.
Claim 18
Dependent Claim
21 words
A programmable integrated circuit logic array device as recited in claim 1 wherein said memory cells are formed using EPROM technology.
Claim 19
Dependent Claim
50 words
A programmable integrated circuit logic array device as recited in claim 1 wherein each said sensing means includes at least one OR gate coupled to a plurality of the cells of a corresponding AND array, and each said AND array has a selectable number of product terms per OR gate.
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