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US4609931A
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Input protection MOS semiconductor device with zener breakdown mechanism
Assignee: Toshiba Corp
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Filing: 1985-06-26
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Granted: 1986-09-02
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Expires: 2005-06-26
Abstract
Abstract A p - -type well region is formed in a n - -type semiconductive substrate. An n-channel metal oxide semiconductor field effect transistor (N-MOSFET) is formed in the p - -type well region. The p - -type well region is electrically insulated from an external potential such as the ground potential. The gate electrode of the N-MOSFET is connected to the p - -type well region. When the N-MOSFET is used as an input protective device of a CMOS integrated circuit, an n + -type layer corresponding to the source electrode of the N-MOSFET is grounded, while another n + -type layer corresponding to the drain electrode thereof is connected to an input terminal of the CMOS integrated circuit through a resistor.
Inventors
- 👤 Hideharu Koike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:31
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
157 words
A semiconductor device to provide overvoltage protection at an input terminal of an integrated circuit, said device comprising: a semiconductor substrate of a first conductivity type and having a first surface portion on which said integrated circuit is formed, and a second surface portion; a semiconductor well region of a second conductivity type formed in said second surface portion of said substrate; and a metal oxide semiconductor field effect transistor formed in said well region and having a grounded source layer of said first conductivity type, a drain layer of said first conductivity type connected to said input terminal, and a gate layer electrically connected to said semiconductor well region, whereby, when an abnormally large voltage appears at the input terminal, Zener breakdown occurs between said well region and said source or drain layer and the well region potential approaches the potential of said drain or source layer according to the polarity of said abnormally large voltage.
Claim 2
Dependent Claim
157 words
A semiconductor device to provide overvoltage protection at an input terminal of an integrated circuit, said device comprising: a semiconductor substrate of a first conductivity type and having a first surface portion on which said integrated circuit is formed, and a second surface portion; a semiconductor well region of a second conductivity type formed in said second surface portion of said substrate; and a metal oxide semiconductor field effect transistor formed in said well region and having a grounded source layer of said first conductivity type, a drain layer of said first conductivity type connected to said input terminal, and a gate layer electrically connected to said semiconductor well region, whereby, when an abnormally large voltage appears at the input terminal, Zener breakdown occurs between said well region and said source or drain layer and the well region potential approaches the potential of said drain or source layer according to the polarity of said abnormally large voltage.
Claim 3
Dependent Claim
39 words
A semiconductor device according to claim 1 further comprising a semiconductive layer of the second conductivity type formed in said well region, and wherein said gate layer of said field effect transistor is directly connected to said semiconductor layer.
Claim 4
Dependent Claim
40 words
A semiconductor device according to claim 2, wherein said device further comprises: an oxide layer formed in said well region between said drain layer and said semiconductor layer; and means for electrically connecting said semiconductor layer to said gate layer.
Claim 5
Dependent Claim
27 words
A semiconductor device according to claim 3, further comprising: a resistor connected between said drain layer of said transistor and said input terminal of said integrated circuit.
Claim 6
Dependent Claim
156 words
A semiconductor device to provide overvoltage protection at an input terminal of an integrated circuit, said device comprising: an Insulating substrate havIng a first surface portion on which said integrated circuit is formed, and a second surface portion; and a metal oxide semiconductor field effect transistor formed in said surface portion of said substrate, said field effect transistor having a grounded source layer of a first conductivity type, a drain layer of the first conductivity type connected to said input terminal, a channel layer of a second condutivity type formed between said source and drain layer on said substrate, and a gate layer electrically connected to said channel layer, whereby, when an abnormally large voltage appears at said input terminal, Zener breakdown occurs between said channel layer and said source or drain layer and the channel layer potential approaches the potential of said drain or source layers, according to the polarity of said abnormally large voltage.
Claim 7
Dependent Claim
156 words
A semiconductor device to provide overvoltage protection at an input terminal of an integrated circuit, said device comprising: an Insulating substrate havIng a first surface portion on which said integrated circuit is formed, and a second surface portion; and a metal oxide semiconductor field effect transistor formed in said surface portion of said substrate, said field effect transistor having a grounded source layer of a first conductivity type, a drain layer of the first conductivity type connected to said input terminal, a channel layer of a second condutivity type formed between said source and drain layer on said substrate, and a gate layer electrically connected to said channel layer, whereby, when an abnormally large voltage appears at said input terminal, Zener breakdown occurs between said channel layer and said source or drain layer and the channel layer potential approaches the potential of said drain or source layers, according to the polarity of said abnormally large voltage.
Claim 8
Dependent Claim
45 words
A semiconductor device according to claim 5, wherein said field effect transistor comprises an insulating layer formed between said gate layer and said channel layer, and said insulating layer having a contact hole through which said gate layer is directly connected to said channel layer.
Claim 9
Dependent Claim
15 words
A semiconductor device according to claim 6, wherein said insulating substrate comprises a sapphire substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |