Patent US4608652A successfully refreshed from Google Patents.
US4608652A
Expired / Lapsed
US
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Method of displaying a logic signal
Assignee: Tektronix Japan Corp
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Filing: 1982-12-10
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Granted: 1986-08-26
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Expires: 2002-12-10
Abstract
Abstract A digital logic signal characterized by a bit sequence is displayed on a raster scan type screen in compressed form. The bit sequence is divided into N+1 bit segments and each bit of each segment, excluding the first bit of each segment, is compared to its preceding bit on a bit-by-bit, segment-by-segment basis. If a bit matches its preceding bit, a bit matching the preceding bit is generated. If a bit does not match its preceding bit, a bit opposite in state to the last bit produced is generated. The generated bits thus comprise a compressed sequence of N bit segments each corresponding to one N+1 bit segment of the original data sequence. A compressed waveform based on the generated sequence is then displayed.
Inventors
- 👤 Hidemi Yokokawa
- 👤 Miyuki Fukuzawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:41
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
157 words
A method of compressing a first binary bit sequence, the method comprising the steps of: comparing a first and a second bit of said first sequence; generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit; and generating an output bit of a state matching said preceding bit whenever any said successive bit and its preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence.
Claim 2
Independent Claim
157 words
A method of compressing a first binary bit sequence, the method comprising the steps of: comparing a first and a second bit of said first sequence; generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit; and generating an output bit of a state matching said preceding bit whenever any said successive bit and its preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence.
Claim 3
Independent Claim
178 words
A method of displaying a representation of a first sequence of binary bits in compressed form, the method comprising the steps of: a. comparing a first and a second bit of said first sequence, generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; b. comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence; and displaying a representation of said second sequence on a display screen.
Claim 4
Independent Claim
178 words
A method of displaying a representation of a first sequence of binary bits in compressed form, the method comprising the steps of: a. comparing a first and a second bit of said first sequence, generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; b. comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence; and displaying a representation of said second sequence on a display screen.
Claim 5
Independent Claim
311 words
A method of compressing a sequence of binary bits, the method comprising the steps of: a. dividing said sequence into a set of bit segments, each segment comprising a plurality of bits; b. comparing a first and a second bit of a first of said bit segments, generating an output bit of a state matching said first bit if said first and second bits of said first segment are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; c. comparing each successive bit of said first segment, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating a output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states; d. comparing a first and a second bit of a next bit segment, generating an output bit of a state matching said first bit if said first and second bits of said successive segment are of a similar state and generating an output bit of a state differing from a last generated output bit if said first and second bits are of differing states; e. comparing each successive bit of said next bit segment to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states; and f. repeating steps d and e for each successive segment of said sequence.
Claim 6
Independent Claim
311 words
A method of compressing a sequence of binary bits, the method comprising the steps of: a. dividing said sequence into a set of bit segments, each segment comprising a plurality of bits; b. comparing a first and a second bit of a first of said bit segments, generating an output bit of a state matching said first bit if said first and second bits of said first segment are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; c. comparing each successive bit of said first segment, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating a output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states; d. comparing a first and a second bit of a next bit segment, generating an output bit of a state matching said first bit if said first and second bits of said successive segment are of a similar state and generating an output bit of a state differing from a last generated output bit if said first and second bits are of differing states; e. comparing each successive bit of said next bit segment to its preceding bit, generating an output bit of a state matching said preceding bit whenever any said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever any said successive bit and its preceding bit are of differing states; and f. repeating steps d and e for each successive segment of said sequence.
Claim 7
Independent Claim
184 words
A method of displaying in compressed form a representation of a binary waveform, the method comprising the steps of: converting said waveform to a plurality of sequences composed of binary bits; comparing a first and a second bit of said first sequence, generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence; and displaying a representation of said second sequence on a cathode ray tube.
Claim 8
Independent Claim
184 words
A method of displaying in compressed form a representation of a binary waveform, the method comprising the steps of: converting said waveform to a plurality of sequences composed of binary bits; comparing a first and a second bit of said first sequence, generating an output bit of a state matching said first bit if said first and second bits are of a similar state and generating an output bit of a first state if said first and said second bits are of differing states; comparing each successive bit of said first sequence, except said first and second bits thereof, to its preceding bit, generating an output bit of a state matching said preceding bit whenever said successive bit and its said preceding bit are of a similar state, and generating an output bit differing in state from a last generated output bit whenever said successive bit and its preceding bit are of differing states, said output bits comprising a second binary bit sequence having one less bit than said first sequence; and displaying a representation of said second sequence on a cathode ray tube.
Claim 9
Dependent Claim
60 words
A method as in claim 4 wherein said second sequence is displayed on said cathode ray tube by converting each successive bit of said second sequence to data suitable for controlling a display attribute of a raster scanning electron beam in said cathode ray tube, said display attribute being controlled according to the state of each said second sequence bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-25 | 1990-02-24 | 1990-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-25 | 1994-02-24 | 1994-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-25 | 1998-02-24 | 1998-08-26 | $7700.00 | Window Closed / Lapsed |