Multiprocessor memory system employing data transfer system

Claim 1

A memory system employing an address bus carrying real address words (RAW), said address bus consisting of two subbuses, a first said sub-bus carrying a real memory part address (RPA) and a second said sub-base carrying a real local address (RLA); a memory having a plurality of memory parts of the same memory size, said memory parts being addressed by said real memory part addresses (RPA) and locations within each of such parts being addressed by said real local addresses (RLA); assembly means connected to said address bus for assembling addresses and connected to said memory for accessing said memory locations, said assembly means comprising an address selector and an address bus selection switch, an associative memory connected to said first said sub-bus and adapted to store a plurality of memory part addresses (PA), and to present said stored memory part addresses (PA) to an output of said associative memory; said address selector having a first input connected to said first sub-bus and a second input connected to the output of said associative memory, said address selector being adapted to supply either of said first and second inputs to its output, said address bus selector switch for selecting between addresses supplied from the address selector or from a processor bus and having a first input connected to the output of said address selector, and a second input connected to said second sub-bus, and an output connected to the address inputs of said memory; said address selector being connected to a control signal and responsive thereto for selecting either its said first or its second input for connection to said address bus switch; and said address selector being connected to said control signal and responsive thereto for supplying to said address bus switch either of its first and second inputs, whereby said memory is accessed either with said real address word (RAW) from said first and second sub-buses of said address bus or with an address word made up of the memory part addresses (PA) produced by said associative memory and said real local address (RLA) from said second sub-bus of said address bus.