US4608583A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FET amplifier
Assignee: Lockheed Martin Corp
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Filing: 1985-10-02
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Granted: 1986-08-26
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Expires: 2005-10-02
Abstract
Abstract High power operation of an amplifier is more easily achieved in the 15 GHz and higher portion of the radio frequency spectrum by utilizing transmission line techniques to form the elements of the amplifier. Source, drain and gate members are arranged as elements of a radio frequency transmission line on a doped, semiconductor surface. When properly biased, the device operates as an amplifier.
Inventors
- 👤 Walter R. Curtice
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:00
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/873; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
257 words
A solid state transmission line, field effect transistor (FET) radio frequency amplifier, said amplifier having an input impedance and an output impedance, comprising: a body of semiconductor material having at least one planar surface; a layer of doped semiconductor material positioned on the planar surface; a plurality of substantially parallel conductive lines formed on the layer of doped material; the plurality of lines arranged on the doped semiconductor layer as radio frequency transmission lines with respect to each other to support at a given wavelength a wave travelling parallel to the longitudinal axes of said lines; said lines having an input section and an output section and being arranged on said layer in spaced sequence, respectively, as a source line, a first rectifying gate line, a second rectifying gate line and a drain line of said FET; said input section of said lines being formed into a tapered transmission line arranged to match the source impedance of an input signal to the input impedance of said amplifier; a signal input means comprising two input terminals connected, respectively, to the first gate line and said source line of said tapered section, said source line being connected to ground; a signal output means connected to said output section of said lines including two output terminals connected, respectively, to the drain line and ground of the output section of said lines; and means for providing an RF ground connection to said second gate line for isolating RF signals on said drain line from RF signals on said first gate line.
Claim 2
Dependent Claim
257 words
A solid state transmission line, field effect transistor (FET) radio frequency amplifier, said amplifier having an input impedance and an output impedance, comprising: a body of semiconductor material having at least one planar surface; a layer of doped semiconductor material positioned on the planar surface; a plurality of substantially parallel conductive lines formed on the layer of doped material; the plurality of lines arranged on the doped semiconductor layer as radio frequency transmission lines with respect to each other to support at a given wavelength a wave travelling parallel to the longitudinal axes of said lines; said lines having an input section and an output section and being arranged on said layer in spaced sequence, respectively, as a source line, a first rectifying gate line, a second rectifying gate line and a drain line of said FET; said input section of said lines being formed into a tapered transmission line arranged to match the source impedance of an input signal to the input impedance of said amplifier; a signal input means comprising two input terminals connected, respectively, to the first gate line and said source line of said tapered section, said source line being connected to ground; a signal output means connected to said output section of said lines including two output terminals connected, respectively, to the drain line and ground of the output section of said lines; and means for providing an RF ground connection to said second gate line for isolating RF signals on said drain line from RF signals on said first gate line.
Claim 3
Dependent Claim
36 words
The amplifier of claim 1, wherein: the source line and drain line are respectively in ohmic contact with the doped material; and the first and second gate lines are in Schottky contact with the doped material.
Claim 4
Dependent Claim
88 words
The amplifier of claim 1, wherein: the drain line has a D.C. bias voltage applied thereto that is positive with respect to the source line; the first gate line has a D.C. bias voltage applied thereto that is negative with respect to the source line; and the second gate line has a D.C. bias voltage applied thereto that is positive with respect to the source line whereby the wave velocity of the signal in the drain-source transmission line can be adjusted to adjust the gain of the amplifier.
Claim 5
Dependent Claim
45 words
The amplifier of claim 3, wherein: the body of semiconductor material is gallium arsenide; and the doped layer is a layer of gallium arsenide doped to a concentration of about 10 17 /cm 3 and has a thickness ranging from about 0.2 to 0.5 microns.
Claim 6
Dependent Claim
34 words
The amplifier of claim 4, wherein: the source and drain lines are comprised of a layer of a AuGe/Ni/Au alloy; and the first and second gate lines are comprised of a layer of Ti/Pt/Au.
Claim 7
Dependent Claim
42 words
The amplifier of claim 3, wherein: the body of semiconductor material is indium phosphide and the doped layer is either doped gallium indium arsenide or indium phosphide; and the doped layer has a thickness ranging from about 0.2 to about 0.5 microns.
Claim 8
Dependent Claim
25 words
An amplifier according to claim 1 further including an additional conductive line positioned adjacent to said drain line and in Schottky contact with said surface.
Claim 9
Dependent Claim
44 words
An amplifier according to claim 1 wherein said isolating means comprises a first capacitor connected between the input end of said second gate line and said ground and a second capacitor connected between the output end of said second gate line and said ground.
Claim 10
Dependent Claim
61 words
An amplifier according to claim 7 further including an impedance matching network comprising: a third capacitor connected to the input section of said drain line between a first and second resistor connected commonly to said capacitor and to the input end of said additional line and said second gate, to thereby reduce standing wave voltages on said drain source transmission line.
Claim 11
Dependent Claim
46 words
An amplifier according to claim 7 further including an impedance matching network comprising grounded resistive termination means for the output section of said second gate line, said first gate line and said source line to thereby reduce standing wave voltages on said gate source transmission line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-25 | 1990-02-24 | 1990-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-25 | 1994-02-24 | 1994-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-25 | 1998-02-24 | 1998-08-26 | $7700.00 | Window Closed / Lapsed |