Removal of line selection artifacts from trace portions of line transfer CCD imager video output signals

Claim 3

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting image elements of a radiant energy image, which charge transfer channels have respective output ports parallelly aligned with each other; a line selector sequentially dynamically clocking said parallelled image register charge transfer channels thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register, said sequential dynamic clocking being for substantially full line duration length of time for each sequential line selection to cause the line selection artifacts to occur in portions of the line scan intervals defining in the time domain a spatial band normal to the direction of line scan and narrower than that spatial band associated with a line retrace interval; a charge funnel having an input port to which the parallelly aligned output ports of said image register charge transfer channels connect and having an output port; a charge sensing stage having an input port for receiving charge packets serially supplied thereto and having an output port for supplying samples of a video signal responsive respectively to those serially received charge packets; and a CCD shift register having an input port connected to the output port of said charge funnel, having an output port connected to the input port of said charge sensing stage, and augmenting the time delay between said image register and said charge sensing stage for placing said spatial band in which line selection artifacts occur within that portion of the time domain defined by the line retrace intervals in the video samples supplied from said charge sensing stage.

Claim 4

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting image elements of a radiant energy image, which charge transfer channels have respective output ports parallelly aligned with each other; a line selector sequentially dynamically clocking said parallelled image register charge transfer channels thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register, said sequential dynamic clocking being for substantially full line duration length of time for each sequential line selection to cause the line selection artifacts to occur in portions of the line scan intervals defining in the time domain a spatial band normal to the direction of line scan and narrower than that spatial band associated with a line retrace interval; a charge funnel having an input port to which the parallelly aligned output ports of said image register charge transfer channels connect and having an output port; a charge sensing stage having an input port for receiving charge packets serially supplied thereto and having an output port for supplying samples of a video signal responsive respectively to those serially received charge packets; and a CCD shift register having an input port connected to the output port of said charge funnel, having an output port connected to the input port of said charge sensing stage, and augmenting the time delay between said image register and said charge sensing stage for placing said spatial band in which line selection artifacts occur within that portion of the time domain defined by the line retrace intervals in the video samples supplied from said charge sensing stage.

Claim 5

A CCD imager according to claim 2, wherein: said CCD shift register exhibits a delay between its input and output ports which equals a full line duration less the delay exhibited by said charge funnel.

Claim 6

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting image elements of a radiant energy image, which charge transfer channels have respective output ports in a parallel alignment with each other; a line selector sequentially dynamically clocking said parallelled image register charge transfer channels thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register, said sequential dynamic clocking being for substantially full line duration length of time for each sequential line selection to cause the line selection artifacts to occur in a portion of the line scan intervals defining in the time domain a spatial band normal to the direction of line scan and narrower than that spatial band associated with a line retrace interval; a plurality of charge funnels, having respective input ports in parallel alignment with each other and the parallel alignment of the output ports of the charge transfer channels in said image register, and having respective output ports; a charge sensing stage having an input port for receiving charge packets serially supplied thereto and having an output port for supplying samples of a video output signal respectively responsive to those serially received charge packets; a delay and merge CCD structure, having a plurality of input ports to which the output ports of said plurality of charge funnels respectively connect, having an output port connected to the input port of said charge sensing stage, and exhibiting equal delays between each of its input ports and its output port, those delays being of a value for augmenting the time delay between said image register and said charge sensing stage for placing said spatial band in which line selection artifacts occur in a portion of the corresponding time domain that is within that portion of the time domain defined by the line retrace intervals in the video sampled supplied from said output charge sensing stage.

Claim 7

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting image elements of a radiant energy image, which charge transfer channels have respective output ports in a parallel alignment with each other; a line selector sequentially dynamically clocking said parallelled image register charge transfer channels thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register, said sequential dynamic clocking being for substantially full line duration length of time for each sequential line selection to cause the line selection artifacts to occur in a portion of the line scan intervals defining in the time domain a spatial band normal to the direction of line scan and narrower than that spatial band associated with a line retrace interval; a plurality of charge funnels, having respective input ports in parallel alignment with each other and the parallel alignment of the output ports of the charge transfer channels in said image register, and having respective output ports; a charge sensing stage having an input port for receiving charge packets serially supplied thereto and having an output port for supplying samples of a video output signal respectively responsive to those serially received charge packets; a delay and merge CCD structure, having a plurality of input ports to which the output ports of said plurality of charge funnels respectively connect, having an output port connected to the input port of said charge sensing stage, and exhibiting equal delays between each of its input ports and its output port, those delays being of a value for augmenting the time delay between said image register and said charge sensing stage for placing said spatial band in which line selection artifacts occur in a portion of the corresponding time domain that is within that portion of the time domain defined by the line retrace intervals in the video sampled supplied from said output charge sensing stage.

Claim 8

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting elements of a radiant energy image, which charge transfer channels have respective output ports in a parallel alignment with each other; a . line selector sequentially dynamically clocking said parallelled image register charge transfer channels, thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register; a CCD shift register, having a plurality of charge transfer stages side-loaded from respective output ports of the image register charge transfer channels, having an output port, and exhibiting differential delay between its various side-loaded charge transfer stages and its output port; a variable-length CCD delay line, having an input port to which the output port of said CCD shift register connects, having an output port connected to an input port of said charge sensing stage, and being operable to compensate for the differential delay in said CCD shift register; and means for progressively adjusting the length of said variable-length CCD delay line scanning line by scanning line.

Claim 9

A CCD imager comprising: an image register, which includes a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting elements of a radiant energy image, which charge transfer channels have respective output ports in a parallel alignment with each other; a . line selector sequentially dynamically clocking said parallelled image register charge transfer channels, thereby to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register; a CCD shift register, having a plurality of charge transfer stages side-loaded from respective output ports of the image register charge transfer channels, having an output port, and exhibiting differential delay between its various side-loaded charge transfer stages and its output port; a variable-length CCD delay line, having an input port to which the output port of said CCD shift register connects, having an output port connected to an input port of said charge sensing stage, and being operable to compensate for the differential delay in said CCD shift register; and means for progressively adjusting the length of said variable-length CCD delay line scanning line by scanning line.

Claim 10

A variable-length CCD delay line comprising: first and second charge transfer channels in parallel juxtaposition for transferring charge packets in a first direction and in a second direction respectively, which first and second directions are opposite to each other; a first succession of storage gate electrodes crossing said first charge transfer channel and receptive of two-phase clocking voltage for inducing storage wells under alternate ones of those storage gate electrodes; a second succession of storage gate electrodes crossing said second charge transfer channel and receptive of two-phase clocking voltages for inducing storage wells under alternate ones of those storage gate electrodes in parallel juxtaposition with the storage wells induced under alternate ones of the gate electrodes in said first succession; means for erecting a respective energy barrier between each pair of successive gate electrodes in said first succession respective to the potential energy level under the storage gate electrode following the barrier in said first direction; means for erecting a respective potential energy barrier, between each pair of successive storage gate electrodes in said second succession respective to the potential energy level under the storage gate electrode following the barrier in said second direction, and between the storage gate electrode in said second succession following the barrier in said second direction and the parallelly juxtaposed storage gate electrode in said first succession; means for introducing charge packets under the initial storage gate electrode in said first succession; means for transferring charge packets from under the final storage gate electrode in said second succession; and means increasing the potential applied to a selected one of the storage gate electrodes in said second succession for controlling the length of said variable length delay line.

Claim 11

A variable-length CCD delay line comprising: first and second charge transfer channels in parallel juxtaposition for transferring charge packets in a first direction and in a second direction respectively, which first and second directions are opposite to each other; a first succession of storage gate electrodes crossing said first charge transfer channel and receptive of two-phase clocking voltage for inducing storage wells under alternate ones of those storage gate electrodes; a second succession of storage gate electrodes crossing said second charge transfer channel and receptive of two-phase clocking voltages for inducing storage wells under alternate ones of those storage gate electrodes in parallel juxtaposition with the storage wells induced under alternate ones of the gate electrodes in said first succession; means for erecting a respective energy barrier between each pair of successive gate electrodes in said first succession respective to the potential energy level under the storage gate electrode following the barrier in said first direction; means for erecting a respective potential energy barrier, between each pair of successive storage gate electrodes in said second succession respective to the potential energy level under the storage gate electrode following the barrier in said second direction, and between the storage gate electrode in said second succession following the barrier in said second direction and the parallelly juxtaposed storage gate electrode in said first succession; means for introducing charge packets under the initial storage gate electrode in said first succession; means for transferring charge packets from under the final storage gate electrode in said second succession; and means increasing the potential applied to a selected one of the storage gate electrodes in said second succession for controlling the length of said variable length delay line.

Claim 12

A variable-length CCD delay line as set forth in claim 6 included in a CCD imager of line transfer type which further includes: an image register with a plurality of parallelled CCD charge transfer channels for successively transporting charge packets formed by photoconverting elements of a radiant energy image, which charge transfer channels have respective ouput ports in parallel alignment with each other; a CCD shift register, having a plurality of charge transfer stages side-loaded from respective output ports of the image register charge transfer channels, and having an output port connected for introducing charge packets under the initial storage gate electrode in said first succession; a charge sensing stage having an input port to which charge packets are transferred from under the final storage gate electrode in said second succession in a spatial band normal to the direction of line scan no wider than that spatial band as would be associated with the line retrace interval; and a line selector sequentially dynamically clocking said parallelled image register charge transfer channels no more than two at a time, so as to provide for sequential scanning of lines of charge packets representative of the intensities of said image elements from said image register with offsets compensating for the delays in said CCD shift registers.

Claim 13

A CCD imager of line-transfer type comprising: an image register with a number of parallelly arranged charge transfer channels with respective output ports, said charge transfer channels each comprising a succession of charge transfer stages for accumulating charge packets descriptive of respective elements of a radiant energy image impinging on said parallelly arrayed charge transfer channels; means for applying forward clocking signals to selected ones of the charge transfer channels in said image register, selection being made according to a predetermined line scanning pattern; a charge sensing stage having an input port and having an output port for delivering video signal samples indicative of the amplitudes of charge packets received at its input port; and an output register having an output port, having input port means for receiving input charge packets from the output ports of each of the charge transfer channels in said image register, and having means for delaying the passage of each charge packet between its introduction through said input port means and its exit through the output port of said output register to the input port of said charge sensing stage, said means for delaying providing delay of duration that is in a range between a positive multiple of full line duration and that multiple as augmented by a line retrace interval.

Claim 14

A CCD imager of line-transfer type comprising: an image register with a number of parallelly arranged charge transfer channels with respective output ports, said charge transfer channels each comprising a succession of charge transfer stages for accumulating charge packets descriptive of respective elements of a radiant energy image impinging on said parallelly arrayed charge transfer channels; means for applying forward clocking signals to selected ones of the charge transfer channels in said image register, selection being made according to a predetermined line scanning pattern; a charge sensing stage having an input port and having an output port for delivering video signal samples indicative of the amplitudes of charge packets received at its input port; and an output register having an output port, having input port means for receiving input charge packets from the output ports of each of the charge transfer channels in said image register, and having means for delaying the passage of each charge packet between its introduction through said input port means and its exit through the output port of said output register to the input port of said charge sensing stage, said means for delaying providing delay of duration that is in a range between a positive multiple of full line duration and that multiple as augmented by a line retrace interval.

Claim 15

A CCD imager of line transfer type as set forth in claim 8 wherein said positive multiple of full line duration is one full line duration.