US4577232A
Expired / Lapsed
US
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Line addressed charge coupled imager
Assignee: Texas Instruments Inc
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Filing: 1984-08-31
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Granted: 1986-03-18
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Expires: 2004-08-31
Abstract
Abstract This specification discloses a CCD imager which includes a line addressing circuit (24) which selectively addresses CCD imaging gates (48). Output signals are clocked under the gates (48) to a buffer register (30) which is constructed in the form of a tree. Signals from under each of the CCD gates (48) travel an identical length path through the buffer register (30) to a charge detection circuit (46) measured by the number of pixels involved. The output signals thus take the same time, or same number of clock pulses, to travel the length of the buffer register (30) to enable all line switching to be accomplished during the horizontal blanking time of a television thus eliminating the switching noise from the television screen.
Inventors
- 👤 Jaroslav Hynecek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:43
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/745; H04N25/701; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
77 words
A charge transfer imager comprising: an array of charge transfer locations arranged in a plurality of rows; a buffer register disposed at one end of each said rows for receiving charge propagated from said rows; output means connected to said buffer register for receiving charge propagated along said buffer register, and the length of the path traveled by each charge along said buffer register to said output means being equal as measured by number of pixels traveled.
Claim 2
Dependent Claim
77 words
A charge transfer imager comprising: an array of charge transfer locations arranged in a plurality of rows; a buffer register disposed at one end of each said rows for receiving charge propagated from said rows; output means connected to said buffer register for receiving charge propagated along said buffer register, and the length of the path traveled by each charge along said buffer register to said output means being equal as measured by number of pixels traveled.
Claim 3
Dependent Claim
38 words
The imager of claim 1 wherein the length of the path traveled by each charge along said buffer register is equal to the length of the charge path along said rows as measured by number of pixels traveled.
Claim 4
Dependent Claim
14 words
The imager of claim 1 wherein said charge transfer locations comprise charge coupled devices.
Claim 5
Dependent Claim
23 words
The imager of claim 3 wherein said charge transfer locations comprise virtual phase charge coupled devices formed with a single level of metalization.
Claim 6
Dependent Claim
33 words
The imager of claim 1 wherein said buffer register is arranged in a tree structure such that each branch of the tree structure has the same number of pixels as each corresponding branch.
Claim 7
Dependent Claim
24 words
The imager of claim 5 wherein adjacent pairs of said rows are disposed adjacent common portions of a first branch of said buffer register.
Claim 8
Dependent Claim
21 words
The imager of claim 6 wherein each pair of said first branches are interconnected with second branches of said buffer register.
Claim 9
Dependent Claim
25 words
The imager of claim 1 and further comprising a line addressing circuit for arbitrarily selecting any one of said rows of said array for read-out.
Claim 10
Dependent Claim
25 words
The imager of claim 1 and further comprising a line addressing circuit for sequentially selecting any one of said rows of said array for read-out.
Claim 11
Dependent Claim
127 words
A charge transfer imager for use with a television system having read-out and blanking cycles comprising: an imaging array having a plurality of rows of CCDs for storing charge in dependence upon incident light; addresssing means for selecting any desired row for read-out; a buffer register disposed adjacent the ends of said rows and having a plurality of paths; means for clocking charge in a selected row from said row and along said buffer register; output means connected to said buffer register for receiving charge clocked through said buffer register along each of said paths; and said buffer register configured such that the same amount of time or number of clock pulses is required to clock along each path of said buffer register to said output means.
Claim 12
Dependent Claim
127 words
A charge transfer imager for use with a television system having read-out and blanking cycles comprising: an imaging array having a plurality of rows of CCDs for storing charge in dependence upon incident light; addresssing means for selecting any desired row for read-out; a buffer register disposed adjacent the ends of said rows and having a plurality of paths; means for clocking charge in a selected row from said row and along said buffer register; output means connected to said buffer register for receiving charge clocked through said buffer register along each of said paths; and said buffer register configured such that the same amount of time or number of clock pulses is required to clock along each path of said buffer register to said output means.
Claim 13
Dependent Claim
22 words
The charge transfer imager of claim 9 wherein said rows are selected for read-out during the blanking cycle of the television system.
Claim 14
Dependent Claim
38 words
The imager of claim 9 wherein the length of the path traveled by each charge along said buffer register is equal to the length of the charge path along said rows as measured by number of pixels traveled.
Claim 15
Dependent Claim
34 words
The imager of claim 9 wherein said buffer register is arranged in a tree structure such that each corresponding branch of the tree structure has the same length as measured in number of pixels.
Claim 16
Dependent Claim
23 words
The imager of claim 12 wherein adjacent pairs of rows are disposed adjacent common portions of a first branch of said buffer register.
Claim 17
Dependent Claim
21 words
The imager in claim 13 wherein each pair of said first branches are interconnected with second branches of said buffer register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |