US4607250A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit adjustment and filter circuit for digital-to-analog converter
Assignee: BURR-BRWN Corp INTENATIONAL AIRPORT INDUSTRIAL PARK TUCSON ARIZONA A CORP OF DE
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Filing: 1985-05-08
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Granted: 1986-08-19
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Expires: 2005-05-08
Abstract
Abstract A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V CC and -V CC includes a circuit for external adjustment of the bit current of a particular bit of the digital-to-analog converter, which circuit produces a constant adjustment current that is summed with that bit current over a wide range of processing parameters and temperature, and requires only a single terminal for connection of an external potentiometer by means of which the bit current is adjusted and a small value filter capacitor for filtering out noise generated by an internal zener diode voltage reference circuit.
Inventors
- 👤 Jimmy R. Naylor
- 👤 Frederick J. Highton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:54
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1057; H03M1/74; H03M1/80; H03M1/808
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
207 words
In a digital to analog converter including i. a plurality of bit circuits, each including a resistor determinative of a bit current for that bit circuit flowing through a current source transistor having an emitter connected to the resistor and a collector connected to a bit current switch circuit responsive to a digital input signal to switch that bit current into a summing conductor, and ii. a reference voltage circuit generating a voltage on a first conductor conducted to the base of a first emitter follower transistor, the voltage and the voltage of the emitter of the first emitter follower transistor having a noise signal; the improvement comprising the combination of: (a) a first resistor coupled between the emitter of the first emitter follower transistor and a first conductor; (b) a second resistor coupled between the first conductor and a second conductor; (c) an external filter capacitor connected to the first conductor, and (d) an external potentiometer connected between the first conductor and the supply voltage conductor and having a variable resistance terminal coupled to the junction between the emitter of the current source transistor and the resistor of a first one of the bit circuits to effectuate adjustment of the bit current of that bit circuit.
Claim 2
Dependent Claim
207 words
In a digital to analog converter including i. a plurality of bit circuits, each including a resistor determinative of a bit current for that bit circuit flowing through a current source transistor having an emitter connected to the resistor and a collector connected to a bit current switch circuit responsive to a digital input signal to switch that bit current into a summing conductor, and ii. a reference voltage circuit generating a voltage on a first conductor conducted to the base of a first emitter follower transistor, the voltage and the voltage of the emitter of the first emitter follower transistor having a noise signal; the improvement comprising the combination of: (a) a first resistor coupled between the emitter of the first emitter follower transistor and a first conductor; (b) a second resistor coupled between the first conductor and a second conductor; (c) an external filter capacitor connected to the first conductor, and (d) an external potentiometer connected between the first conductor and the supply voltage conductor and having a variable resistance terminal coupled to the junction between the emitter of the current source transistor and the resistor of a first one of the bit circuits to effectuate adjustment of the bit current of that bit circuit.
Claim 3
Dependent Claim
39 words
In a digital-to-analog converter, the improvement of c1aim 1 including a third resistor coupled between the second conductor and a third conductor, the resistance of the first resistor being less than the resitances of the second and third resistors.
Claim 4
Dependent Claim
39 words
In a digital-to-analog converter, the improvement of c1aim 1 including a third resistor coupled between the second conductor and a third conductor, the resistance of the first resistor being less than the resitances of the second and third resistors.
Claim 5
Dependent Claim
45 words
In a digital to analog converter, the improvement of claim 2 including an external resistor coupled between the variable resistance terminal of the external potentiometer and the junction between the emitter of the current source transistor and the precision resistor of the first bit circuit.
Claim 6
Dependent Claim
41 words
In a digital to analog converter, the improvement of claim 3 including a second emitter follower transistor having its emitter coupled to a fourth resistor and to the bases of the current source transistors of a plurality of the bit circuits.
Claim 7
Dependent Claim
30 words
In a digital to analog converter, the improvement of claim 4 wherein the current source transistors, the first emitter follower transistor, and the second emitter follower transistors are NPN transistors.
Claim 8
Dependent Claim
39 words
In a digital to analog converter, the improvement of claim 5 wherein a V BE multiplier circuit and a zener diode circuit cooperate to cause the bit currents to be substantially independent of temperature over a predetermined temperature range.
Claim 9
Dependent Claim
35 words
In a digital-to-analog converter, the improvement of claim 4 wherein the resistance of the potentiometer is sufficiently high that changes in current through the potentiometer do not significantly change the voltage on the first conductor.
Claim 10
Dependent Claim
32 words
In a digital-to-analog converter, the improvement of claim 7 wherein the first resistor and the external filter capacitor form a low pass filter to effectively filter any noise from the first conductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-18 | 1990-02-17 | 1990-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-18 | 1994-02-17 | 1994-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-18 | 1998-02-17 | 1998-08-19 | $7700.00 | Window Closed / Lapsed |