Use of implant process for programming ROM type processor for encryption

Claim 2

A data processing device implemented on a single semiconductor substrate comprising: a central processing means for performing data processing operations upon data in accordance with encrypted instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored in a specified address location; a control read only memory connected to said central processing unit having stored therein microcode for generation of control signals for control of said central processing unit in response to said encrypted instructions, whereby the data processing operation corresponding to a particular instruction is unknown without knowledge of the contents of said control read only memory, said control read only memory including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; a read only memory means having a plurality of address locations which are a subset of the possible address locations of said at least one memory access operation, for storing at respective address locations data and encrypted instructions which define data processing operations; an information transfer means connected to said central processing means and said read only memory means for transfer of data and instructions; and an external interface means connected to said information transfer means for providing information from said information transfer means to at least one device external to said single semiconductor substrate.

Claim 3

A data processing device as claimed in claim 1, wherein: said read only memory means includes a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device and wherein said encrypted instructions stored in said read only memory means includes a deciphering program for deciphering enciphered programs received via said enternal interface means.

Claim 4

A data processing device formed on a single semiconductor substrate comprising: a central processing means for performing data processing operations upon data in accordance with instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored in a specified address location; a control read only memory connected to said central processing unit having stored therein microcode for generation of control signals for control of said central processing unit in response to said instructions, said control read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; a read only memory means having a plurality of address locations which are a subset of the possible address locations of said at least one memory access operation, for storing data and instructions which define data processing operations at respective address locations, said read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an information transfer means connected to said central processing means and said read only memory means for transfer of data and instructions; an external interface means connected to said information transfer means for providing information to at least one device external to said single semiconductor substrate; at least one security bit memory means, each for storing therein a single bit of data indicating a secure state when said read only memory means is to be secure or a nonsecure state; an address logic means connected to said information transfer bus for generating a protected access signal when a memory access operation specifies one of said address locations of said read only memory means; and an external interface inhibit logic means connected to said at least one security bit memory means, said external interface means and said address logic means for inhibiting said external interface means thereby preventing transfer of information to said at least one external device when any of said at least one security bit memory means indicates said secure state and said address logic means generates said protected access signal.

Claim 5

A data processing device formed on a single semiconductor substrate comprising: a central processing means for performing data processing operations upon data in accordance with instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored in a specified address location; a control read only memory connected to said central processing unit having stored therein microcode for generation of control signals for control of said central processing unit in response to said instructions, said control read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; a read only memory means having a plurality of address locations which are a subset of the possible address locations of said at least one memory access operation, for storing data and instructions which define data processing operations at respective address locations, said read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an information transfer means connected to said central processing means and said read only memory means for transfer of data and instructions; an external interface means connected to said information transfer means for providing information to at least one device external to said single semiconductor substrate; at least one security bit memory means, each for storing therein a single bit of data indicating a secure state when said read only memory means is to be secure or a nonsecure state; an address logic means connected to said information transfer bus for generating a protected access signal when a memory access operation specifies one of said address locations of said read only memory means; and an external interface inhibit logic means connected to said at least one security bit memory means, said external interface means and said address logic means for inhibiting said external interface means thereby preventing transfer of information to said at least one external device when any of said at least one security bit memory means indicates said secure state and said address logic means generates said protected access signal.

Claim 6

A data processing device formed on a single semiconductor substrate as claimed in claim 3, wherein: said instructions stored in said read only memory are encrypted instructions; and said control read only memory generates control signals for control of said central processing unit in response to said instructions, whereby the data processing operations corresponding to a paricular instruction is unknown without knowledge of the contents of said control read only memory.

Claim 7

A data processing device formed on a single semiconductor substrate comprising: a read only memory means having a first plurality of address locations storing at respective address locations data and instructions which define data processing operations, said read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an electrically programmable memory means having a second plurality of address locations for storing at respective address locations data and instructions which define data processing operations; a central processing means connected to said read only memory means and said electrically programmable memory means for performing data processing operations upon data in accordance with instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored at a specified address location including said first and second plurality of address locations; a control read only memory connected to said central processing unit having stored therein microcode for generation of control signals for control of said central processing unit in response to said instructions, said control read only memory including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an information transfer means connected to said read only memory means, said electrically programmable memory means and said central processing means for transfer of data and instructions; an external interface means connected to said information transfer means for providing information to at least one device external to said single semiconductor substrate; at least one security bit memory means, each for storing therein a single bit of data indicating a secure state when said electrically programmable memory means is to be secure or a nonsecure state; an address logic means connected to said information transfer bus for generating a protected access signal when a memory access operation specifies one of said address locations of said electrically programmable memory means; and an external interface inhibit logic means connected to said at least one security bit memory means, said external interface means and said address logic means for inhibiting said external interface means thereby preventing transfer of information to said at least one external device when any of said at least one security bit memory means indicates said secure state and said address logic means generates said protected access signal.

Claim 8

A data processing device formed on a single semiconductor substrate comprising: a read only memory means having a first plurality of address locations storing at respective address locations data and instructions which define data processing operations, said read only memory means including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an electrically programmable memory means having a second plurality of address locations for storing at respective address locations data and instructions which define data processing operations; a central processing means connected to said read only memory means and said electrically programmable memory means for performing data processing operations upon data in accordance with instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored at a specified address location including said first and second plurality of address locations; a control read only memory connected to said central processing unit having stored therein microcode for generation of control signals for control of said central processing unit in response to said instructions, said control read only memory including a plurality of field effect transistors for storing individual bits, each field effect transistor having a gate, a source, a drain and a channel region disposed between said source and drain and underneath said gate, said channel region of selected ones of said field effect transistors having impurities implanted therein to prevent conduction between said source and drain regardless of the signal on said gate thereby determining the data bit stored in said field effect device; an information transfer means connected to said read only memory means, said electrically programmable memory means and said central processing means for transfer of data and instructions; an external interface means connected to said information transfer means for providing information to at least one device external to said single semiconductor substrate; at least one security bit memory means, each for storing therein a single bit of data indicating a secure state when said electrically programmable memory means is to be secure or a nonsecure state; an address logic means connected to said information transfer bus for generating a protected access signal when a memory access operation specifies one of said address locations of said electrically programmable memory means; and an external interface inhibit logic means connected to said at least one security bit memory means, said external interface means and said address logic means for inhibiting said external interface means thereby preventing transfer of information to said at least one external device when any of said at least one security bit memory means indicates said secure state and said address logic means generates said protected access signal.

Claim 9

A data processing device formed on a single semiconductor substrate as claimed in claim 5, wherein: said instructions stored in said read only memory are encrypted instructions; and said control read only memory generates control signals for control of said central processing unit in response to said instructions, whereby the data processing operations corresponding to a paricular instruction is unknown without knowledge of the contents of said control read only memory.

Claim 10

A data processing device formed on a single semiconductor substrate as claimed in claim 5, wherein: said data processing device further includes a read/write memory means connected to said central processing unit; said read only memory means has instructions forming a deciphering program stored therein for deciphering enciphered programs received via said enternal interface means; and said central processing unit is responsive to said deciphering program stored in said read only memory means and said enciphered programs received from said external interface means for storing a deciphered program in said read/write memory means.

Claim 11

A data processing device formed on a single semiconductor substrate as claimed in claim 5, wherein: said data processing device further includes a read/write memory means connected to said central processing unit; said electrically programmable memory means has instructions forming a deciphering program stored therein for deciphering enciphered programs received via said enternal interface means; and said central processing unit is responsive to said deciphering program stored in said electrically programmable memory means and said enciphered programs received from said external interface means for storing a deciphered program in said read/write memory means.