Gated solid state FET relay

Claim 2

A solid state relay circuit for switching power to an electrical load (10) comprising; a load lead (12) for connection to the electrical load (10), a positive supply lead (16) for connection to a source of positive electrical potential, a control signal lead (18), an N-channel MOS-FET (20) having drain (22) and source (24) and gate (26) terminals with said drain terminal (22) connected to said positive power supply lead (16) and said source terminal (24) connected to said load lead (12), characterized by gated oscillator means (36) receiving power from said power supply lead (16) and connected to said control signal lead (18) and having an output terminal and for oscillating to produce a voltage at said output terminal and to cease oscillating to terminate voltage at said output terminal in response to electrical signals on said control signal lead (18), and voltage multiplier means (28, 30, 32, 34) interconnecting said oscillator output terminal and said gate (26) of said MOS-FET (20) for multiplying said output voltage from said oscillator means (36) for driving said MOS-FET (20) into conduction to power the load during oscillation of said oscillation means (36).

Claim 3

A circuit as set forth in claim 1 further characterized by said voltage multiplier including first (28) and second (30) diodes a first (32) and second (34) capacitors, said first diode (28) having its output combined with the output of said oscillator means (36) and being supplied electrical power in response to said electrical signals on said control signal lead (18).

Claim 4

A circuit as set forth in claim 2 further characterized by including amplifier means (38) interconnecting said control signal lead (18) and said power supply lead (16) and said gated oscillator means (36) for amplifying low level input voltages on said control signal lead (18) to a sufficient driving voltage level at an output (50) thereof.

Claim 5

A circuit as set forth in claim 3 further characterized by said first diode (28) being supplied power from the output (50) of said amplifier (38).

Claim 6

A circuit as set forth in either one of claims 1, 2, 3, or 4 further characterized by including signal discharge means (70, 72) interconnecting said gate (26) of said MOS-FET (20) and a negative electrical potential (14) and responsive to electrical signals on said control signal lead (18) for positive and stable turn off of said MOS-FET (20) in the absence of an electrical signal on said control signal lead (18) sufficient for circuit operation.

Claim 7

A solid state relay circuit for switching power to an electrical load (10) comprising: a load lead (12) for connection to the electrical load (10); a positive supply lead (16) for connection to a source of positive electrical potential; a source of negative electrical potential (14); a control signal lead (18) for carrying electrical signals to turn the circuit on and off for supplying power to the load (10) when on and terminating power to the load (10) when off; and N-channel MOS-FET (20) having a drain (22) and source (24) and gate (26) terminals with said drain terminal (22) connected to said positive power supply lead (16) and said source terminal (24) connected to said load lead (12); characterized by a first transistor (40) interconnecting said control signal lead (18), said positive electrical potential (16), and said negative electrical potential (14); a first integrated circuit means (48) interconnecting said first transistor (40) and said positive (16) and negative (14) electrical potentials for inverting the output of said first transistor (40) to provide a level-shifting stage output (50); a gated free running square wave oscillator means (52) receiving said level-shifting stage output (50) for producing a square wave output; voltage multiplier means (28, 30, 32, 34) for multiplying the voltage of said square wave output from said oscillator means and applying same to said gate (26) of said MOS-FET (20) for driving said MOS-FET (20) into conduction to supply electrical power to said load (10) in response to electrical signals on said control signal lead (18); and a second transistor (70) interconnecting said gate (26) of said MOS-FET (20), and said negative electrical potential (14) and said level-shifting stage output (50) to pull said gate (26) of said MOS-FET (20) to said negative electrical potential (14) in the absence of a signal at said level shifting stage output (50).

Claim 8

A solid state relay circuit for switching power to an electrical load (10) comprising: a load lead (12) for connection to the electrical load (10); a positive supply lead (16) for connection to a source of positive electrical potential; a source of negative electrical potential (14); a control signal lead (18) for carrying electrical signals to turn the circuit on and off for supplying power to the load (10) when on and terminating power to the load (10) when off; and N-channel MOS-FET (20) having a drain (22) and source (24) and gate (26) terminals with said drain terminal (22) connected to said positive power supply lead (16) and said source terminal (24) connected to said load lead (12); characterized by a first transistor (40) interconnecting said control signal lead (18), said positive electrical potential (16), and said negative electrical potential (14); a first integrated circuit means (48) interconnecting said first transistor (40) and said positive (16) and negative (14) electrical potentials for inverting the output of said first transistor (40) to provide a level-shifting stage output (50); a gated free running square wave oscillator means (52) receiving said level-shifting stage output (50) for producing a square wave output; voltage multiplier means (28, 30, 32, 34) for multiplying the voltage of said square wave output from said oscillator means and applying same to said gate (26) of said MOS-FET (20) for driving said MOS-FET (20) into conduction to supply electrical power to said load (10) in response to electrical signals on said control signal lead (18); and a second transistor (70) interconnecting said gate (26) of said MOS-FET (20), and said negative electrical potential (14) and said level-shifting stage output (50) to pull said gate (26) of said MOS-FET (20) to said negative electrical potential (14) in the absence of a signal at said level shifting stage output (50).

Claim 9

A circuit as set forth in either claim 1 or 6 further characterized by including slow turn-on resistor means (74) for slowly driving said MOS-FET (20) into conduction.

Claim 10

A circuit as set forth in either claim 1 or further characterized by including slow turn off resistor means (76) for slowly decreasing and terminating the conduction of said MOS-FET (20).

Claim 11

A circuit as set forth in claim 6 further characterized by said voltage multiplier means including first (28) and second (30) diodes and first (32) and second (34) capacitors, said first diode (28) having an output combined with said square wave output of said oscillator means and being supplied power from said level-shifting stage output (50).

Claim 12

A circuit as set forth in claim 9 further characterized by including gate discharge integrated circuit means (72) interconnecting said level-shifting stage output (50) and said second transistor (70) for converting the level-shifting stage output (50) so that said second transistor (70) is driven into conduction from said gate (26) of said MOS-FET (20) to said negative electrical potential (14) in response to a lack of output at said level-shifting stage output (50).

Claim 13

A circuit as set forth in claim 10 further characterized by including third (60) and fourth (62) diodes and associated resistors (64, 66, 68) interconnecting said control signal lead (18), said negative electrical potential (14) and said first transistor (40) for establishing a minimum voltage level for driving said first transistor (40) into conduction.

Claim 14

A circuit as set forth in claim 11 further characterized by including a zener diode (46) and current limiting resistor (44) for providing over-voltage protection between said positive power supply lead (16) and said first transistor (40).

Claim 15

A circuit as set forth in claim 6 further characterized by including a slow turn off resistor (76) disposed between said gate (26) of said MOS-FET (20) and said second transistor (70) for slowly decreasing and terminating conduction of said MOS-FET (20).

Claim 16

A circuit as set forth in claim 9 further characterized by said first capacitor (32) disposed between said oscillator means (36) and the junction of said first (28) and second (30) diodes and second capacitor (34) being disposed between said negative electrical potential (14) and the output of said second diode (30), a slow turn on resistor (74) disposed between said second diode (30) and said second capacitor (34) for controlling the voltage buildup across said second capacitor (34).