Low offset single ended MOS comparator

Claim 2

In an integrated MOS comparator circuit having first and second input nodes and an output node, the improvement comprising a biasing circuit comprising a first pair of series connected MOS devices, a second pair of series connected MOS devices, each of said pairs of devices being connected between a source of voltage and ground, one device of said first pair having a gate electrode adapted to be connected with an input voltage, one device of said second pair having a gate electrode adapted to be connected with a reference voltage, the junction between said first pair of devices connected to said first node, the gate electrodes of the other device in each of said pairs being connected to said second node and to a junction between the second pair of devices, said second pair of device being sized to produce a voltage at said second input node which is equal to the voltage at said output node when said input voltage equals said reference voltage.

Claim 3

In an integrated MOS comparator circuit having an input node, a reference node and an output node and comprising first, second and third stages, each including a depletion device and an enhancement device, the output node of the comparator circuit being connected to at least one inverter amplifier stage including a depletion device having source and gate coupled together to produce a zero source to gate differential voltage, the improvement comprising a biasing circuit means responsive to an input voltage V in and a reference voltage V ref for biasing said first, second and third stages so as to produce a zero source to gate differential voltage at each depletion device thereof when Vin equals V ref .

Claim 4

In an integrated MOS comparator circuit having an input node, a reference node and an output node and comprising first, second and third stages, each including a depletion device and an enhancement device, the output node of the comparator circuit being connected to at least one inverter amplifier stage including a depletion device having source and gate coupled together to produce a zero source to gate differential voltage, the improvement comprising a biasing circuit means responsive to an input voltage V in and a reference voltage V ref for biasing said first, second and third stages so as to produce a zero source to gate differential voltage at each depletion device thereof when Vin equals V ref .

Claim 5

In an integrated MOS comparator circuit having first, second, third and fourth stages, each stage comprising a depletion device and an enhancement device connected in series between a source of voltage and ground, the gate electrode of the enhancement devices of said first and second stages being connected to a first node between the devices of the first stage, the gate electrode of the enhancement device of the third stage being connected to a second node between the devices of the second stage, the gate electrode of the depletion devices of the second and third stages connected together and providing a level shifted reference node, the gate electrode of the depletion device of the first stage providing a level shifted input node and the junction between the devices of the third stage providing an output node, the gate electrode of the enhancement device of the fourth stage connected to said output node, the depletion device of said fourth stage having its gate connected to its source to provide a zero gate to source differential, the improvement comprising a biasing circuit including fifth and sixth stages, each comprising a depletion device connected in series with an enhancement device, the gate electrode of the enhancement device of said fifth and sixth stages being connected to said level shifted reference node and to a third node between the depletion and enhancement devices of said fifth stage, the junction between the depletion and enhancement devices of said sixth stage being connected to said input node, the gate electrode of the depletion devices of said fifth and sixth stages adapted to be respectively connected to a reference voltage and to an input voltage, the depletion and enhancement devices of said fifth stage being sized to produce a voltage at said level shifted reference node which is equal to the voltage at said output node when said input voltage is equal to said reference voltage.

Claim 6

In an integrated MOS comparator circuit having first, second, third and fourth stages, each stage comprising a depletion device and an enhancement device connected in series between a source of voltage and ground, the gate electrode of the enhancement devices of said first and second stages being connected to a first node between the devices of the first stage, the gate electrode of the enhancement device of the third stage being connected to a second node between the devices of the second stage, the gate electrode of the depletion devices of the second and third stages connected together and providing a level shifted reference node, the gate electrode of the depletion device of the first stage providing a level shifted input node and the junction between the devices of the third stage providing an output node, the gate electrode of the enhancement device of the fourth stage connected to said output node, the depletion device of said fourth stage having its gate connected to its source to provide a zero gate to source differential, the improvement comprising a biasing circuit including fifth and sixth stages, each comprising a depletion device connected in series with an enhancement device, the gate electrode of the enhancement device of said fifth and sixth stages being connected to said level shifted reference node and to a third node between the depletion and enhancement devices of said fifth stage, the junction between the depletion and enhancement devices of said sixth stage being connected to said input node, the gate electrode of the depletion devices of said fifth and sixth stages adapted to be respectively connected to a reference voltage and to an input voltage, the depletion and enhancement devices of said fifth stage being sized to produce a voltage at said level shifted reference node which is equal to the voltage at said output node when said input voltage is equal to said reference voltage.