Dual validity bit arrays

Claim 2

Apparatus for producing a first binary number of "n" bits from a second binary number of "m" bits, the lower order "a" bits of the second binary number being an index number and the higher order "b" bits of the second binary number being a key number, comprising: an associative random access memory having 2 a addressable memory locations, said associative memory adapted to store b+n bits at each addressable memory location; a first independently addressable validity bit array random access memory having 2 a addressable memory locations, said first array adapted to store a validity bit at each addressable memory location; a second independently addressable validity bit array random access memory having a 2 a addressable memory locations, said second array adapted to store a validity bit at each addressable memory location; pointer means for enabling only one of said validity bit arrays to receive address signals of "a" bits at a given time from the binary number m and to produce the validity bit stored at an addressed memory location; circuit means for applying to the associative memory and to the enabled validity bit array the lower "a" bits of the second number as an address, said associative memory in response thereto and to a read enable signal for producing signals representing the (b+n) bits stored at the addressed location of the associative memory, and the enabled validity bit array in response thereto and to a read enable signal producing a signal representing the validity bit stored at the addressed location of the enabled validity bit array; circuit means for comparing the signals representing higher order "b" bits of the second number and the "b" bits stored at the addressed location of the associative memory and for producing a signal that the "n" signals representing a first binary number produced by the associative memory is correct if the signals representing the higher order "b" bits of said second number and the "b" bits of the key number compare and the validity bit produced by the enabled validity bit array is set; means for resetting all the validity bits of all addressable locations stored in the not enabled validity bit array; and means responsive to a CAMP-instruction control signal for causing the pointer to disable the then enabled array and to enable the then disabled array after all validity bits of the not enabled validity bit array have been reset.

Claim 3

Apparatus as defined in claim 1 in which the first binary number is a physical page number and in which the second binary number is a virtual page number.

Claim 4

Apparatus as defined in claim 2 in which n equals 16, m equals 36, a equals 10, and b equals 26.

Claim 5

Apparatus as defined in claim 3 in which the pointer means includes a J-K F/F.

Claim 6

Apparatus as defined in claim 3 in which the means for resetting all validity bits of all addressed locations stored in a not enabled validity bit array includes a counter capable of producing the address of each memory location of an array during one cycle of operation when enabled.

Claim 7

Apparatus as defined in claim 5 in which the means responsive to a clear-associative-memory control signal is inhibited from enabling the then disabled array while the counter is enabled to produce addreses during one of the counter's cycles of operation.

Claim 8

A paging buffer for producing a physical page number of 16 bits derived from a virtual page number of 36 bits, the lower order 10 bits of which are a lower virtual page number and the higher order 26 bits of which are an upper virtual page number, comprising: an associative random access memory having 2 10 addressable memory locations, the address of each of which is associated with a lower virtual page number and which associative memory is adapted to store a 26-bit key and a 16-bit target physical page number; a first independently addressable validity bit array random access memory having 2 10 addressable memory locations, the address of each location being a lower virtual page number and adapted for storing a validity bit; a second independently addressable validity bit array random access memory having a 2 10 addressable memory locations, the address of each location being a lower virtual page number and adapted for storing a validity bit; pointer means for enabling one of said validity bit arrays to receive address signals of a lower virtual page number of a given virtual address and for disabling the other array from receiving said address signals; circuit means for applying to the directly mapped associative random access memory and to the enabled validity bit array address signals corresponding to the lower virtual page number of said given virtual page number, said associative memory in response thereto and to a read enable signal producing signals representing the key and the target physical page number bits stored at the addressed location of the associative memory and the enabled validity bit array in response thereto and to a read enable signal producing a signal representing the validity bit stored at the addressed location; circuit means to which signals representing the upper virtual page number of the virtual page number is applied for comparing the signals representing the upper virtual page number of the virtual page number and the 26 bits of the key stored at the addressed location of the associative memory and for producing a signal representing that the physical page number produced by the paging buffer is correct if the upper virtual page number and the key compare, and the validity bit is set; means for clearing the disabled validity bit array by resetting all the validity bits stored in the disabled validity bit array; and means responsive to a clear associative memory signal for causing the pointer to disable the enabled array and to enable the disabled array after being cleared.

Claim 9

A paging buffer for producing a physical page number of 16 bits derived from a virtual page number of 36 bits, the lower order 10 bits of which are a lower virtual page number and the higher order 26 bits of which are an upper virtual page number, comprising: an associative random access memory having 2 10 addressable memory locations, the address of each of which is associated with a lower virtual page number and which associative memory is adapted to store a 26-bit key and a 16-bit target physical page number; a first independently addressable validity bit array random access memory having 2 10 addressable memory locations, the address of each location being a lower virtual page number and adapted for storing a validity bit; a second independently addressable validity bit array random access memory having a 2 10 addressable memory locations, the address of each location being a lower virtual page number and adapted for storing a validity bit; pointer means for enabling one of said validity bit arrays to receive address signals of a lower virtual page number of a given virtual address and for disabling the other array from receiving said address signals; circuit means for applying to the directly mapped associative random access memory and to the enabled validity bit array address signals corresponding to the lower virtual page number of said given virtual page number, said associative memory in response thereto and to a read enable signal producing signals representing the key and the target physical page number bits stored at the addressed location of the associative memory and the enabled validity bit array in response thereto and to a read enable signal producing a signal representing the validity bit stored at the addressed location; circuit means to which signals representing the upper virtual page number of the virtual page number is applied for comparing the signals representing the upper virtual page number of the virtual page number and the 26 bits of the key stored at the addressed location of the associative memory and for producing a signal representing that the physical page number produced by the paging buffer is correct if the upper virtual page number and the key compare, and the validity bit is set; means for clearing the disabled validity bit array by resetting all the validity bits stored in the disabled validity bit array; and means responsive to a clear associative memory signal for causing the pointer to disable the enabled array and to enable the disabled array after being cleared.

Claim 10

In combination: associative memory means having "n" storage locations where "n" is an integer greater than zero, each storage location for storing a key field and a target field, bits of the key field of each storage location being a predetermined set of bits obtained from a virtual address and bits of the target field of each storage location being a physical address where the virtual address from which the set of bits stored in the key field were obtained; a first and a second validity bit array, each array having "n" storage locations for storing a validity bit for the key and target fields stored in the associative memory means at the locations having the same address, each validity bit having two values, a first value denoting that the key and target fields stored in the locations having the same address are valid and a second value when either or both are invalid; means for enabling one validity bit array and for disabling the others; means for applying to the enabled array address signals of "n" bits which signals are also applied to the associative memory means; means for writing validity bits into the addressed locations of the enabled bit array and for reading validity bits from the addressed locations of the enabled validity bit array; means for writing validity bits of the second value into each memory location of the disabled validity bit array; and means responsive to a clear associative memory means instruction for enabling the disabled array and for disabling the enabled array after validity bits of the second value have been written into all memory locations of the disabled array.

Claim 11

In combination: associative memory means having "n" storage locations where "n" is an integer greater than zero, each storage location for storing a key field and a target field, bits of the key field of each storage location being a predetermined set of bits obtained from a virtual address and bits of the target field of each storage location being a physical address where the virtual address from which the set of bits stored in the key field were obtained; a first and a second validity bit array, each array having "n" storage locations for storing a validity bit for the key and target fields stored in the associative memory means at the locations having the same address, each validity bit having two values, a first value denoting that the key and target fields stored in the locations having the same address are valid and a second value when either or both are invalid; means for enabling one validity bit array and for disabling the others; means for applying to the enabled array address signals of "n" bits which signals are also applied to the associative memory means; means for writing validity bits into the addressed locations of the enabled bit array and for reading validity bits from the addressed locations of the enabled validity bit array; means for writing validity bits of the second value into each memory location of the disabled validity bit array; and means responsive to a clear associative memory means instruction for enabling the disabled array and for disabling the enabled array after validity bits of the second value have been written into all memory locations of the disabled array.

Claim 12

The combination of claim 8 in which "n" equals 2 10 .

Claim 13

The combination of claim 9 in which the predetermined set of bits obtained from the virtual address is an upper virtual page number (UVPN).

Claim 14

The combination of claim 10 in which the address signals applied to the enabled validity bit array is the lower virtual page number of the virtual address.