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US4602324A
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Digital control system
Assignee: Bendix Corp
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Filing: 1983-02-16
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Granted: 1986-07-22
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Expires: 2003-02-16
Abstract
Abstract An electronic control (10) for generating control, diagnostic, and fault signals for a diesel engine (12) with a turbocharger (22) and an injection pump (14). The control (10) provides an injection pump control (78), a turbocharger control (80), a fault monitor (82) and a sequencing control (84). These controllers are embodied as a stored program of a microprocessor controlled processor, timing, and memory module (228). The module (228) communicates with an input section receiving analog and discrete inputs via a serial input data line (CRUIN) and further communicates with an output section generating analog and discrete outputs via a serial output data line (CRUOUT).
Inventors
- 👤 Charles S. Fujawa
- 👤 David J. Argyelan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:06
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/24; F02D41/26; F02D41/266; F02D41/30; F02D41/38; F02B; F02B3/00; F02B3/06; F02D41/22; F02D2041/224; F02D2041/226
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
349 words
A digital control system having a processor for executing a program sequence stored in a memory, said processor and memory communicating with each other through a data bus, an address bus, and a control bus, said processor further provided with a serial input data line, a serial output data line, and a serial data clock line, said system further comprising: an input section including an analog input multiplexer and a discrete input multiplexer, said analog input multiplexer having a plurality of analog input channels individually connectable to a single analog output and means, responsive to a channel address, for selecting the analog input channel connected to the output; an analog to digital converter having a plurality of digital data outputs for representing a converted analog parameter, an analog input for receiving said analog parameter connected to the output of said analog input multiplexer, a conversion request line for initiating an analog to digital conversion, and an additional digital output line for indicating when a conversion has been completed; a parallel to serial converter responsive to a selection signal, having a plurality of digital inputs connected to the digital outputs of said analog to digital converter and operable to shift the bits on its inputs onto a serial output line which is connected to said serial data input line of said processor; an input multiplexer control for generating said channel address for said analog input multiplexer, said conversion request for said analog to digital converter, said selection signal for said parallel to serial converter, and a selection signal for said discrete input multiplexer from information on said address bus and said serial data clock line; an output section including a serial to parallel converter having a data input connected to said output data line of the processor and a plurality of digital outputs individually connectable to said data input, and further having means, responsive to an output channel address, for selecting the digital output connected to said input; an output multiplexer control for generating said output channel addresses from information on said address bus and said serial data clock line.
Claim 2
Dependent Claim
349 words
A digital control system having a processor for executing a program sequence stored in a memory, said processor and memory communicating with each other through a data bus, an address bus, and a control bus, said processor further provided with a serial input data line, a serial output data line, and a serial data clock line, said system further comprising: an input section including an analog input multiplexer and a discrete input multiplexer, said analog input multiplexer having a plurality of analog input channels individually connectable to a single analog output and means, responsive to a channel address, for selecting the analog input channel connected to the output; an analog to digital converter having a plurality of digital data outputs for representing a converted analog parameter, an analog input for receiving said analog parameter connected to the output of said analog input multiplexer, a conversion request line for initiating an analog to digital conversion, and an additional digital output line for indicating when a conversion has been completed; a parallel to serial converter responsive to a selection signal, having a plurality of digital inputs connected to the digital outputs of said analog to digital converter and operable to shift the bits on its inputs onto a serial output line which is connected to said serial data input line of said processor; an input multiplexer control for generating said channel address for said analog input multiplexer, said conversion request for said analog to digital converter, said selection signal for said parallel to serial converter, and a selection signal for said discrete input multiplexer from information on said address bus and said serial data clock line; an output section including a serial to parallel converter having a data input connected to said output data line of the processor and a plurality of digital outputs individually connectable to said data input, and further having means, responsive to an output channel address, for selecting the digital output connected to said input; an output multiplexer control for generating said output channel addresses from information on said address bus and said serial data clock line.
Claim 3
Dependent Claim
144 words
A digital control system as defined in claim 1, wherein said input multiplexer control includes: a channel selection device for generating said channel address to said analog input multiplexer; said channel selection device having a digital input connected to said serial output data line, a plurality of digital outputs connected to said analog input multiplexer, an enable input connected to said serial data clock, and a plurality of address selection inputs connected to said address buss; wherein the processor is adapted to provide a channel selection word in serial format synchronously with the data clock, each bit of said channel selection word being steered to one of the outputs of said channel selection device by enabling said enable input with said data clock and by sequentially changing the information on the address lines to the locations assigned said outputs of said channel selection device.
Claim 4
Dependent Claim
103 words
A digital control system as defined in claim 2, wherein said input multiplexer control includes: means for generating said conversion request including a D-bistable device generating said conversion request as one of it output states, said D-bistable device having a clock input connected to said serial data clock line and its D-input connected to said serial data output line; wherein the processor is adapted to provide a serial data clock signal on said serial data clock line and a conversion request bit on said output data line synchronously with said data clock signal to cause the D-bistable device to generate said conversion request.
Claim 5
Dependent Claim
36 words
A digital control system as defined in claim 1, wherein said input multiplexer control includes: gating circuitry, responsive to selected states on said address buss, for generating a selection signal which enables said discrete input multiplexer.
Claim 6
Dependent Claim
33 words
A digital control system as defined in claim 2, wherein: said data clock signal being gated to said enable input through a gate having an enable input responsive to a state selection signal.
Claim 7
Dependent Claim
28 words
A digital control system as defined in claim 5, wherein: said state selection signal is generated by a state selection device responsive to information on said address lines.
Claim 8
Dependent Claim
33 words
A digital control system as defined in claim 3, wherein: said data clock signal is gated to said clock input through a gate having an enable input responsive to a state selection signal.
Claim 9
Dependent Claim
28 words
A digital control system as defined in claim 7, wherein: said state selection signal is generated by a state selection device responsive to information on said address lines.
Claim 10
Dependent Claim
98 words
A digital control system as defined in claim 1, wherein said input multiplexer control includes: a channel selection device for generating said channel address to said analog input multiplexer in response to a first state selection signal; means for generating said conversion request to said analog to digital converter in response to a second state selection signal; means for generating said selection signal to said discrete input multiplexer in response to a fourth state selection signal; and state selection means, responsive to information on said address buss, for generating said first, second, third, and fourth state selection signals.
Claim 11
Dependent Claim
61 words
A digital control system as defined in claim 9, wherein: the processor generates a first address word on the address bus to cause the state selection means to generate said first state selection signal and generates a serial channel address word on the data output line to said channel selection device thereby enabling a particular channel of said analog input multiplexer.
Claim 12
Dependent Claim
48 words
A digital control system as defined in claim 10, wherein: the processor generates a second address word in the address bus and a conversion bit on said output data line to cause the state selection means to generate said second state selection signal, thereby generating said conversion request.
Claim 13
Dependent Claim
65 words
A digital control system as defined in claim 11, wherein: the processor generates a third address word on the address bus, in response to the input data line signaling an analog to digital conversion has been accomplished, to cause the state selection means to generate said third state selection signals, thereby serializing the output of the analog to digital converter on said input data line.
Claim 14
Dependent Claim
49 words
A digital control system as defined in claim 12, wherein: the processor generates a fourth address word on the address bus to cause said state selection means to generate said fourth state selection signal thereby serializing the discrete inputs of said discrete input multiplexer onto said input data line.
Claim 15
Dependent Claim
80 words
A digital control system as defined in claim 1, wherein said serial to parallel converter comprises: a plurality of output multiplexer devices, each having a single data input connectable to a plurality of data outputs, said connection being responsive to a selection signal to an enabling input of the device and an output address signal indicative of a particular data output; wherein all of said data inputs of said output multiplexer devices are connected commonly with said output data line.
Claim 16
Dependent Claim
39 words
A digital control system as defined in claim 14, wherein said output multiplexer control includes: means, responsive to said output channel address, for generating said selection signal to said output multiplexer devices in synchronism with said data clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |