Semiconductor memory device

Claim 2

A semiconductor memory device for providing a writing or erasing operation, comprising: a plurality of column lines; a plurality of row lines; a column decoder, operatively connected to said column lines, for selecting one of said column lines; a row decoder, operatively connected to said row lines, for selecting one of said row lines; a plurality of memory cells, one of said memory cells being accessed by a selected one of said column lines and a selected one of said row lines; a clock generator for producing clock pulses; a voltage supply for supplying a high voltage; and a plurality of charge pump circuits, respectively, operatively connected to said column lines and said row lines and operatively connected to said clock generator and said voltage supply, for increasing the voltage on said selected ones of said column and row lines to the high voltage of said voltage supply during the writing or erasing operation, each of said charge pump circuits comprising: a capacitor, operatively connected to said clock generator, charging and discharging in response to the clock pulses from said clock generator; a charge transfer transistor, operatively connected to said capacitor, for transferring charge from said voltage supply to said column or row line connected thereto, in response to the charge on said capacitor; and gate means, operatively connected between said clock generator and said capacitor, for cutting off said capacitor, if said column or row line connected to said respective charge pump circuit is unselected, from said clock generator.

Claim 3

A device as claimed in claim 1, wherein each of said gate means comprises a first transistor operatively connected between said clock generator said said capacitor, said first transistor being on when said column or row line connected to said respective charge pump circuit is selected and being off when said column or row line connected to said respective charge pump circuit is unselected.

Claim 4

A device as claimed in claim 2, wherein said charge transfer transistor in each of said charge pump circuits has a gate connected to said respective column or row line.

Claim 5

A device as claimed in claim 3, wherein said column and row decoders supply a source voltage to said selected ones of said column and row lines and ground said unselected column and row lines.

Claim 6

A device as claimed in claim 4, wherein said device further comprises a plurality of second transistors, operatively connected between said column decoder and said column lines and between said row decoder and said row lines, said second transistors being off only when one of said column lines and one of said row lines connected thereto are selected during the writing and erasing operations so as to cut off the selected ones of said column and row lines from said column and row decoders, respectively.

Claim 7

A device as claimed in claim 1, wherein said device further comprises a plurality of transistors operatively connected between said column decoder and said column lines and between said row decoder and said row lines, said transistors being off only when one of said column lines and one of said row lines connected thereto are selected during the writing and erasing operations so as to cut off the selected ones of said column and row lines from said column and row decoders, respectively.

Claim 8

A device as claimed in claim 6, wherein each of said memory cells includes: a selection transistor, operatively connected to said memory cells, for selecting said memory cells; and a memory transistor, operatively connected to said selection transistor, for storing information.

Claim 9

A device as claimed in claim 1, wherein each of said memory cells comprises: a selection transistor, operatively connected to said memory cells, for selecting said memory cells; and a memory transistor, operatively connected to said selection transistor, for storing information.

Claim 10

A semiconductor memory device, operatively connectable to receive a supply voltage, for providing a writing or erasing operation, comprising: column lines; row lines; a column decoder, operatively connected to said column lines, for selecting one of said column lines; a row decoder, operatively connected to said row lines, for selecting one of said row lines; memory cells, operatively connected to said column lines and said row lines, one of said memory cells being accessed by a selected one of said column lines and a selected one of said row lines; a clock generator for producing clock pulses; a voltage multiplier, operatively connected to receive the supply voltage and operatively connected to said clock generator, for supplying a voltage higher than the supply voltage; and charge pump circuits, respectively, operatively connected to said column and row lines and operatively connected to said clock generator and said voltage multiplier, for increasing the voltage on said selected ones of said column and row lines to the high voltage of said voltage multiplier during the writing or erasing operation, each of said charge pump circuits comprising: a capacitor, operatively connected to said clock generator, for charging and discharging in response to the clock pulses from said clock generator; a charge transfer transistor, operatively connected to said capacitor and said voltage multiplier, for transferring charge from said voltage multiplier to said column or row line connected thereto, in response to the charge on said capacitor; and gate means, operatively connected between said clock generator and said capacitor, for cutting off said capacitor, in said charge pump circuits connected to an unselected column or row line, from said clock generator.

Claim 11

A semiconductor memory device, operatively connectable to receive a supply voltage, for providing a writing or erasing operation, comprising: column lines; row lines; a column decoder, operatively connected to said column lines, for selecting one of said column lines; a row decoder, operatively connected to said row lines, for selecting one of said row lines; memory cells, operatively connected to said column lines and said row lines, one of said memory cells being accessed by a selected one of said column lines and a selected one of said row lines; a clock generator for producing clock pulses; a voltage multiplier, operatively connected to receive the supply voltage and operatively connected to said clock generator, for supplying a voltage higher than the supply voltage; and charge pump circuits, respectively, operatively connected to said column and row lines and operatively connected to said clock generator and said voltage multiplier, for increasing the voltage on said selected ones of said column and row lines to the high voltage of said voltage multiplier during the writing or erasing operation, each of said charge pump circuits comprising: a capacitor, operatively connected to said clock generator, for charging and discharging in response to the clock pulses from said clock generator; a charge transfer transistor, operatively connected to said capacitor and said voltage multiplier, for transferring charge from said voltage multiplier to said column or row line connected thereto, in response to the charge on said capacitor; and gate means, operatively connected between said clock generator and said capacitor, for cutting off said capacitor, in said charge pump circuits connected to an unselected column or row line, from said clock generator.