Banked memory circuit

Claim 2

A memory circuit for interconnection to a data processor having a central processing unit, said memory circuit being adapted to add additional memory storage to said data processor comprising in combination: a plurality of memory banks, each bank including memory means for storage of information; a bank selection circuit means connected to said central processing unit for receiving information from the data processor indicating a selected one of the memory banks, and responsive to a timing signal generated by said central processing unit responsive to the operating sequence of said central processing unit; and memory access means for alternating access between the selected memory bank and a specific memory bank.

Claim 3

A memory circuit according to claim 1 further including memory refresh means for providing only one refresh signal to each memory bank during a single refresh time period, said refresh time period including a plurality of time intervals during which at least one memory bank receives a refresh signal.

Claim 4

A memory circuit according to claim 2 wherein said memory access means provides data from said specific memory bank on a dedicated output path.

Claim 5

A memory circuit according to claim 3 wherein each memory means of each memory bank includes a memory location for each memory address of the data processor.

Claim 6

A memory circuit according to claim 4 wherein said memory refresh means generates the refresh signal in accordance with a plurality of signals from a display means.

Claim 7

A memory circuit according to claim 5 wherein the specific memory bank contains information storage locations dedicated for access by said display means.

Claim 8

A memory circuit for interconnection with a data processor, to externally add additionally memory storage useable by said data processor and under control of said data processor and wherein said data processor generates at least one timing signal responsive to the timing sequence of the operation of said data processor, said memory circuit comprising: a plurality of memory banks, each memory bank including memory means for storage of information for said data processor; a bank selection circuit connected to the data processor for receiving data representing a selected one of said plurality of memory banks; and memory access means for alternating access between the selected memory bank and a specific memory bank in accordance with said timing signal from said data processor.

Claim 9

A memory circuit for interconnection with a data processor, to externally add additionally memory storage useable by said data processor and under control of said data processor and wherein said data processor generates at least one timing signal responsive to the timing sequence of the operation of said data processor, said memory circuit comprising: a plurality of memory banks, each memory bank including memory means for storage of information for said data processor; a bank selection circuit connected to the data processor for receiving data representing a selected one of said plurality of memory banks; and memory access means for alternating access between the selected memory bank and a specific memory bank in accordance with said timing signal from said data processor.

Claim 10

A memory circuit according to claim 7 wherein said specific memory bank includes information storage for a dedicated application circuit of said data processor.

Claim 11

A memory circuit according to claim 8 wherein said dedicated application circuit is a display means for providing the output of information to a data processor user.

Claim 12

A memory circuit according to claim 9 wherein said timing signal indicates access of the memory circuit by the dedicated application circuit.

Claim 13

A memory circuit according to claim 10 wherein said timing signal indicates a access of the memory circuit by the display means.

Claim 14

A memory circuit according to claim 1 further including memory refresh means for providing a refresh signal to said memory banks in accordance with a plurality of signals from the display means.

Claim 15

A memory circuit for interconnection with a data processor to externally add memory storage useable by said data processor under control of said data and wherein said data processor generates at least one timing signal responsive to the sequence of operation of the data processor, said memory circuit comprising: data interface means for transmitting and receiving data information from said data processor; address interface means for transmitting and receiving address information from the data processor; a plurality of memory banks, each bank including memory means for storage of information and each connected to said data interface means and said address interface means; memory banks selection means for receiving at least one signal from said data processor indicating a selected memory bank for access; memory access means for providing access signals to the plurality of memory banks providing access to the stored information in response to control signals received from said data processor, said access means alternating access between the selected memory bank and a specific memory bank in response to said timing signal from said data processor indicating a memory access by a dedicated circuit; and memory refresh means for providing a single refresh signal to each memory bank during a refresh time period which consists of a plurality of individual time intervals where during each interval at least one memory bank receives its refresh signal.

Claim 16

A memory circuit for interconnection with a data processor to externally add memory storage useable by said data processor under control of said data and wherein said data processor generates at least one timing signal responsive to the sequence of operation of the data processor, said memory circuit comprising: data interface means for transmitting and receiving data information from said data processor; address interface means for transmitting and receiving address information from the data processor; a plurality of memory banks, each bank including memory means for storage of information and each connected to said data interface means and said address interface means; memory banks selection means for receiving at least one signal from said data processor indicating a selected memory bank for access; memory access means for providing access signals to the plurality of memory banks providing access to the stored information in response to control signals received from said data processor, said access means alternating access between the selected memory bank and a specific memory bank in response to said timing signal from said data processor indicating a memory access by a dedicated circuit; and memory refresh means for providing a single refresh signal to each memory bank during a refresh time period which consists of a plurality of individual time intervals where during each interval at least one memory bank receives its refresh signal.

Claim 17

A memory circuit according to claim 13 wherein each memory means includes a memory location for each address location of the data processor.

Claim 18

A memory circuit according to claim 14 wherein said memory refresh means provides the refresh signal in response to a plurality of signals from said dedicated circuit.

Claim 19

A memory circuit according to claim 15 further including an output interface means for transmitting the stored information of the memory means to the dedicated circuit.

Claim 20

A memory circuit according to claim 16 wherein said specific memory bank includes memory locations dedicated to the storage of information for the dedicated circuit.

Claim 21

A memory circuit according to claim 17 wherein said dedicated circuit is a memory means for the display of output information to a user.

Claim 22

A memory circuit according to claim 18 further including a reset circuit means connected to receive a power signal from the data processor and for providing a reset signal to the memory circuit for initializing the memory circuit at a delayed time interval after the reception of the power signal.