US4600951A — Scanning sample, signal generation, data digitizi…

Claim 1

Independent Claim 150 words

A system for generating timing signals in spaced synchronism with the movement of a laser beam comprising: means for sweeping the laser beam across a swept space; means for dividing the sweeping laser beam into a major portion and a minor portion, the major portion swept across the swept space; an optical grating positioned in the path swept by the minor portion; a photosensor for generating timing signals from the portion of the laser beam that passes through the optical grating; a filter for blocking components of the timing signals that are in a frequency band outside of a predetermined frequency range; a circuit tuned to oscillate at twice the frequency of the predetermined frequency range, said circuit receiving the signals that pass through the filter, the tuned circuit having sufficient ringing capability to continue oscillating with substantial energy for a plurality of cycles absent signals passing through the filter.

Claim 2

Independent Claim 150 words

A system for generating timing signals in spaced synchronism with the movement of a laser beam comprising: means for sweeping the laser beam across a swept space; means for dividing the sweeping laser beam into a major portion and a minor portion, the major portion swept across the swept space; an optical grating positioned in the path swept by the minor portion; a photosensor for generating timing signals from the portion of the laser beam that passes through the optical grating; a filter for blocking components of the timing signals that are in a frequency band outside of a predetermined frequency range; a circuit tuned to oscillate at twice the frequency of the predetermined frequency range, said circuit receiving the signals that pass through the filter, the tuned circuit having sufficient ringing capability to continue oscillating with substantial energy for a plurality of cycles absent signals passing through the filter.

Claim 3

Dependent Claim 232 words

A data stream speed-reduction and duty-cycle-improvement system comprising: a first random access memory having address inputs; a data input and a data output; a first binary counter, in the first mode counting timing signals and in the second mode counting clock pulses, having outputs connected to the address inputs of the first random access memory; a second random access memory having address inputs; a data input and a data output; a second binary counter, in the first mode counting clock signals and in the second mode counting timing signals, having outputs connected to the address inputs of the second random access memory; means for generating timing signals at the first, higher frequency; clock means for generating clock signals at the second, lower frequency; a bistable circuit, stable in either a "1" state or a "0" state, having facility for changing state when alternation is required; a first plurality of steering gates, enabled when the bistable circuit is in the "1" state for conveying timing signals from the timing signal generating means to the first counter and clock signals from the clock signal generating means to the second counter; and a second plurality of steering gates, enabled when the bistable circuit is in the "0" state for conveying timing signals from the timing signal generating means to the second counter and clock signals from the clock signal generating means to the first counter.

Claim 4

Dependent Claim 232 words

A data stream speed-reduction and duty-cycle-improvement system comprising: a first random access memory having address inputs; a data input and a data output; a first binary counter, in the first mode counting timing signals and in the second mode counting clock pulses, having outputs connected to the address inputs of the first random access memory; a second random access memory having address inputs; a data input and a data output; a second binary counter, in the first mode counting clock signals and in the second mode counting timing signals, having outputs connected to the address inputs of the second random access memory; means for generating timing signals at the first, higher frequency; clock means for generating clock signals at the second, lower frequency; a bistable circuit, stable in either a "1" state or a "0" state, having facility for changing state when alternation is required; a first plurality of steering gates, enabled when the bistable circuit is in the "1" state for conveying timing signals from the timing signal generating means to the first counter and clock signals from the clock signal generating means to the second counter; and a second plurality of steering gates, enabled when the bistable circuit is in the "0" state for conveying timing signals from the timing signal generating means to the second counter and clock signals from the clock signal generating means to the first counter.

Claim 5

Dependent Claim 28 words

A system according to claim 14 further comprising means responsive to the first plurality of a group of timing signals for changing the state of the bistable circuit.

Claim 6

Dependent Claim 164 words

A data stream speed-reduction and duty-cycle-improvement system comprising: first memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency; second memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency; means for alternating between a first mode and a second mode, in the first mode for causing the first memory means to store data while causing the second memory means to read out data, in the second mode for causing the second memory means to store data while causing the first memory means to read out data; means for generating timing signals at the first, higher frequency; clock means for generating clock signals at the second, lower frequency; and means responsive to the clock signal generating means for controlling the frequency of the timing signals generated by the timing signal generating means.

Claim 7

Dependent Claim 164 words

A data stream speed-reduction and duty-cycle-improvement system comprising: first memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency; second memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency; means for alternating between a first mode and a second mode, in the first mode for causing the first memory means to store data while causing the second memory means to read out data, in the second mode for causing the second memory means to store data while causing the first memory means to read out data; means for generating timing signals at the first, higher frequency; clock means for generating clock signals at the second, lower frequency; and means responsive to the clock signal generating means for controlling the frequency of the timing signals generated by the timing signal generating means.

Claim 8

Dependent Claim 112 words

A system according to claim 16 wherein the controlling means comprises: means responsive to the output of the clock signal generating means for generating drive signals at a frequency that is a fraction of the frequency of the clock signals; a synchronous motor driven by the drive signal generating means at a speed which is in synchronism with the clock signals; a source of focused energy; means driven by the motor for modulating the focused energy in synchronism with the clock signals; and means for sensing the modulated energy and for controlling the operation of the timing signal generating means in response to the frequency at which the focused energy is modulated.

Claim 9

Dependent Claim 84 words

A system according to claim 17 wherein the modulating means comprises: a drum connected for rotation with the motor, the drum being positioned to intercept at its periphery, the focused energy; a plurality of mirrors on the periphery of the drum, positioned to reflect the focused energy, whereby rotation of the mirrored drum sweeps the reflected, focused energy in a path; and means located in the path swept by the focused energy for alternately blocking and passing the focused energy to the sensing means.

Claim 10

Dependent Claim 146 words

A data stream speed-reduction and duty-cycle improvement system comprising: a first memory for receiving, storing, and transmitting data seriatim; a second memory for receiving, storing, and transmitting data seriatim; means for generating timing signals having a frequency corresponding to the rate at which data are received by the memories; means for generating clock signals having a frequency corresponding to the rate at which data are transmitted by the memories; routing means for controlling the routing of the timing signals alternately to the first and second memories and of the clock signals alternately to the second and first memories; means responsive to the first plurality of a group of timing signals for causing the routing means to reverse the routing of the timing signals and the clock signals; and means responsive to the clock signals for controlling the frequency of the means for generating the timing signals.

Claim 11

Dependent Claim 146 words

A data stream speed-reduction and duty-cycle improvement system comprising: a first memory for receiving, storing, and transmitting data seriatim; a second memory for receiving, storing, and transmitting data seriatim; means for generating timing signals having a frequency corresponding to the rate at which data are received by the memories; means for generating clock signals having a frequency corresponding to the rate at which data are transmitted by the memories; routing means for controlling the routing of the timing signals alternately to the first and second memories and of the clock signals alternately to the second and first memories; means responsive to the first plurality of a group of timing signals for causing the routing means to reverse the routing of the timing signals and the clock signals; and means responsive to the clock signals for controlling the frequency of the means for generating the timing signals.

Claim 12

Dependent Claim 78 words

A system according to claim 19 wherein the first memory comprises: a first random access memory and a first counter, the output of the first counter being arranged to address the location in the first random access memory in a predetermined sequence; and the second memory comprises a second random access memory and a second counter, the output of the second counter being arranged to address the locations in the second random access memory in a predetermined sequence.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1989-07-14	1990-01-13	1990-07-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1993-07-14	1994-01-13	1994-07-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1997-07-14	1998-01-13	1998-07-15	$7700.00	Window Closed / Lapsed

Scanning sample, signal generation, data digitizing and retiming system

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