Gate-turn-off thyristor failure detecting circuit

Claim 2

A gate-turn-off thyristor failure detecting circuit comprising: an off-gate signal source; a pulse amplifier connected to said off-gate signal source for amplifying the off-gate signal; a pulse transformer having primary and secondary windings, said primary winding being connected to said pulse amplifier; a gate pulse synthesizing circuit for producing a gate pulse which is applied to a gate of the gate-turn-off thyristor, said gate pulse synthesizing circuit being connected to said secondary winding of said pulse transformer; means for detecting a signal flowing through said primary winding of said pulse transformer; and means for comparing the output signal from said detecting means with a predetermined value to produce an output signal from said comparing means indicative of the failure of the gate-turn-off thyristor.

Claim 3

The gate-turn-off thyristor failure detecting circuit according to claim 1 further comprising: circuit means for generating a test off-gate signal, said generating cirucit means being connected to the primary winding of said pulse amplifier.

Claim 4

The gate-turn-off thyristor failure detecting circuit according to claim 2 wherein said off-gate signal source and said test off-gate signal generating means are connected to said pulse amplifier through an OR circuit.

Claim 5

The gate-turn-off thyristor failure detecting circuit according to claim 1 wherein said signal detecting means is a current detector.

Claim 6

The gate-turn-off thyristor failure detecting circuit according to claim 1 wherein said gate pulse synthesizing circuit also receives an on-gate pulse signal and a bias signal.

Claim 7

A gate-turn-off thyristor failure detecting circuit for detecting the failure of one or more units in a plurality of interconnected gate-turn-off thyristors, the circuit comprising: an off-gate signal source; a plurality of pulse amplifiers each connected to said off-gate signal source for amplifying the off-gate signal; a plurality of pulse tansformers each having primary and secondary windings, each of said primary windings being connected to a different one of said pulse amplifiers; a plurality of gate pulse synthesizing circuits each for producing a gate pulse which is applied to a gate of a different one of the interconnected gate-turn-off thyristors, each of said gate pulse synthesizing circuits being connected to the secondary winding of a different one of said pulse transformers; a plurality of means for detecting a signal flowing through said primary winding of a different one of said pulse transformers; and means connected with each of said plurality of detecting means for comparing the output signals from said plurality of detecting means with a predetermined value to produce an output signal from said comparing means indicative of the failure of one or more gate-turn-off thyristors.

Claim 8

A gate-turn-off thyristor failure detecting circuit for detecting the failure of one or more units in a plurality of interconnected gate-turn-off thyristors, the circuit comprising: an off-gate signal source; a plurality of pulse amplifiers each connected to said off-gate signal source for amplifying the off-gate signal; a plurality of pulse tansformers each having primary and secondary windings, each of said primary windings being connected to a different one of said pulse amplifiers; a plurality of gate pulse synthesizing circuits each for producing a gate pulse which is applied to a gate of a different one of the interconnected gate-turn-off thyristors, each of said gate pulse synthesizing circuits being connected to the secondary winding of a different one of said pulse transformers; a plurality of means for detecting a signal flowing through said primary winding of a different one of said pulse transformers; and means connected with each of said plurality of detecting means for comparing the output signals from said plurality of detecting means with a predetermined value to produce an output signal from said comparing means indicative of the failure of one or more gate-turn-off thyristors.

Claim 9

The gate-turn-off thyristor failure detecting circuit according to claim 6 further comprising: cirucit means for generating a test off-gate signal, said generating circuit means being connected to the primary windings of each of said pulse amplifiers.

Claim 10

The gate-turn-off thyristor failure detecting circuit according to claim 6 wherein said off-gate signal source and said test off-gate signal generating means are connected to the primary windings of each of said pulse amplifiers through an OR circuit.