Patent US4600890A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4600890A Expired / Lapsed US ⏱️ 0.0 years remaining

Demodulator comprising a phase-locked loop

Assignee: US Philips Corp
•
Filing: 1985-01-23
•
Granted: 1986-07-15
•
Expires: 2005-01-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Phase or frequency demodulator comprising an automatic gain control circuit (100), a phase-locked loop (200) and, optionally, a shaping circuit (300) for shaping the output signal of the loop. A feedback path is provided between the output of the loop, or of the signal-shaping circuit, and the automatic gain control circuit, via an automatic noise control circuit (400) for producing an analog signal, the amplitude of which is proportional to the rate at which the loop is temporarily disabled.

Inventors

  • 👤 Philippe Horvat

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 22:09
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052; H03D; H03D3/00; H03D3/02; H03D3/24; H03D3/241; H03D3/244; H04; H04N; H04N5/00; H04N5/44; H04N5/455

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 87 words
A phase or frequency demodulator comprising an automatic gain control circuit for producing from a non-controlled incoming carrier wave, a modulated signal of a constant average level, and a phase-locked loop for producing a demodulated signal from said modulated signal characterized in that said demodulator further comprises an automatic noise control circuit, arranged in a feedback path between said loop and said automatic gain control circuit, for producing an analog signal, an amplitude of which is proportional to the rate at which the loop is temporarily disabled.
Claim 2
Dependent Claim 87 words
A phase or frequency demodulator comprising an automatic gain control circuit for producing from a non-controlled incoming carrier wave, a modulated signal of a constant average level, and a phase-locked loop for producing a demodulated signal from said modulated signal characterized in that said demodulator further comprises an automatic noise control circuit, arranged in a feedback path between said loop and said automatic gain control circuit, for producing an analog signal, an amplitude of which is proportional to the rate at which the loop is temporarily disabled.
Claim 3
Dependent Claim 61 words
A demodulator as claimed in claim 1, characterized in that the automatic noise control circuit comprises a circuit for clamping synchronizing pulses, contained in said carrier wave, onto a lower level thereof, a comparator circuit having a reference level substantially equal to the lower level, and a circuit for measuring the rate of the negative pulses decreasing to below this threshold.
Claim 4
Dependent Claim 88 words
A demodulator as claimed in claim 1, characterized in that the automatic noise control circuit comprises a circuit for clamping synchronizing pulses, contained in said carrier wave, onto a lower level thereof, a circuit for suppressing these pulses, a comparator circuit having two predetermined reference levels lower than or equal to this lower level and higher than a so-called white level, respectively, and a circuit for measuring the rate of the negative pulses which fall below the lower reference level and positive pulses exceeding the higher reference level.
Claim 5
Dependent Claim 67 words
A demodulator as claimed in claim 1, characterized in that the automatic noise control circuit comprises a clamping circuit for clamping synchronizing pulses, contained in said carrier wave, onto a higher level, commonly denoted as the white level, a comparator circuit having a reference level at least equal to said higher level, and a circuit for measuring the rate of the positive pulses exceeding the reference level.
Claim 6
Dependent Claim 26 words
A demodulator as claimed in claim 2, 3 or 4, characterized in that the pulse rate measuring circuit comprises a counter followed by a digital-to-analog converter.

References Cited (Backward Citations)

US4146843A Cited
US4156195A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-07-14 1990-01-13 1990-07-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-07-14 1994-01-13 1994-07-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-07-14 1998-01-13 1998-07-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag