Patent US4599573A successfully refreshed from Google Patents.
US4599573A
Expired / Lapsed
US
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Switched capacitor filter utilizing a differential input and output circuit and method
Assignee: Intel Corp
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Filing: 1985-05-28
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Granted: 1986-07-08
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Expires: 2005-05-28
Abstract
Abstract An integrated circuit employing a differential amplifier and switched capacitor networks to provide filtering techniques. The differential amplifier utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier and a second switched capacitor network coupled to the outputs of the amplifier provide the requisite filtering necessary for analog-to-digital encoding or digital-to-analog decoding. The differential configuration allows for less noise and better power supply rejection, whereby allowing for a higher signal-to-noise ratio.
Inventors
- 👤 Daniel Senderowicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:20
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/005; H03F3/45; H03F3/45071; H03F3/45479; H03H; H03H19/00; H03H19/004; H03F2200/00; H03F2200/372
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
237 words
A power amplifier circuit with a gain setting capability independent of frequency and having, a sin x/x distortion correction characteristic, where x is a function of time, comprising: a switched capacitor differential integrator having differential inputs and differential outputs; a first feedback network coupled between a positive input of said differential inputs and said outputs; said first network including a first capacitor having a value C u , a second capacitor having a value C 2 , a third capacitor having a value C um and a fourth capacitor having a value C 2m , said first and third capacitors being switched, said second and fourth capacitors being non-switched, said first and second capacitors for setting frequency response, said third and fourth capacitors for setting gain; a second network including a fifth capacitor having a value C u , a sixth capacitor having a value C 2 , a seventh capacitor having a value C um and an eighth capacitor having a value C 2m , said fifth and seventh capacitors being switched, and said sixth and eighth capacitors being non-switched, said fifth and sixth capacitors for setting frequency response, said seventh and eighth capacitors for setting gain; wherein gain can be arbitrarily set by two resistors coupled between a common mode terminal and said differential outputs, and wherein gain setting will not affect the frequency response of said amplifier circuit provided that: C.sub.u /C.sub.um =C.sub.2 /C.sub.2m
Claim 2
Dependent Claim
237 words
A power amplifier circuit with a gain setting capability independent of frequency and having, a sin x/x distortion correction characteristic, where x is a function of time, comprising: a switched capacitor differential integrator having differential inputs and differential outputs; a first feedback network coupled between a positive input of said differential inputs and said outputs; said first network including a first capacitor having a value C u , a second capacitor having a value C 2 , a third capacitor having a value C um and a fourth capacitor having a value C 2m , said first and third capacitors being switched, said second and fourth capacitors being non-switched, said first and second capacitors for setting frequency response, said third and fourth capacitors for setting gain; a second network including a fifth capacitor having a value C u , a sixth capacitor having a value C 2 , a seventh capacitor having a value C um and an eighth capacitor having a value C 2m , said fifth and seventh capacitors being switched, and said sixth and eighth capacitors being non-switched, said fifth and sixth capacitors for setting frequency response, said seventh and eighth capacitors for setting gain; wherein gain can be arbitrarily set by two resistors coupled between a common mode terminal and said differential outputs, and wherein gain setting will not affect the frequency response of said amplifier circuit provided that: C.sub.u /C.sub.um =C.sub.2 /C.sub.2m
Claim 3
Dependent Claim
21 words
The amplifier circuit of claim 1 wherein said integrator includes an internal differential signal path and a common mode signal path.
Claim 4
Dependent Claim
79 words
The amplifier circuit of claim 2 wherein said integrator further includes a, first and second differential amplifiers having parallel inputs, outputs of said second differential amplifier being coupled through current mirrors to add to the outputs of said first differential amplifier; two output buffers, one for each output of said first differential amplifier, said buffers also coupled to the outputs of said current mirrors; and a common mode input coupled in series between said first and second differential amplifiers.
References Cited (Backward Citations)
US4453130A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |