Phase detector with independent offset correction

Claim 2

An automatic offset nulling circuit coimprising, phase detector circuit means (110, 111) for receiving a variable input signal and a reference input signal and producing a pair of output signals (Q1, Q2,) representative of the time and phase difference between the respective input signals, offset correction circuit means (114, 115, 118, 119) connected for receiving said pair of output signals from said phase detector means and selectively producing a pair of offset correction signals (Q3, Q4) representative of the time and phase difference relationship between said pair of output signals from said phase detector circuit means, and combining means (120, 121, 122, 123, 113) connected to receive said pair of output signals (Q1, Q2) from said phase detector circuit means and said offset correction signals (Q3, Q4) from said offset correction circuit means to produce a signal (OUT) representative of the combination of said pair of output signals from said phase detector circuit means and said offset correction signals from said offset correction circuit means.

Claim 3

The circuit recited in claim 1 wherein, said phase detector circuit means comprises bistable circuit means.

Claim 4

The circuit recited in claim 1 wherein, said combining means includes difference amplifier means.

Claim 5

The circuit recited in claim 1 wherein, said offset correction circuit means comprises bistable circuit means.

Claim 6

The circuit recited in claim 4 including, delay means connected between an output of said phase detector circuit means and the input of said bistable circuit means.

Claim 7

The circuit recited in claim 4 including, filter means connected between said bistable circuit means and said combining means.

Claim 8

The circuit recited in claim 4 wherein, said bistable circuit means comprises flip-flop means.

Claim 9

The circuit recited in claim 1 wherein, said combining means includes first summing means (120, 121) connected for combining one of said output signals (Q1) from said phase detector means and one of said offset correction signals (Q3) from said offset correction circuit means, and second summing means (122, 123) connected for combining the other of said output signals (Q2) from said phase detector circuit means and the other of said offset correction signals (Q4) from said offset correction circuit means.

Claim 10

The circuit recited in claim 1 wherein, said phase detector circuit means is a dual flip-flop phasefrequency detector.

Claim 11

The circuit recited in claim 6 wherein, said filter means comprise low pass filter circuits.

Claim 12

The circuit recited in claim 1 including, reset means comprising a NAND gate connected to receive said pair of output signals from said phase detector circuit means and to selectively reset said phase detector means in response to said first pair of output signals.

Claim 13

A phase detector circuit with an automatic offset null, comprising, phase detector means for detecting the time and phase difference between a pair of input signals (Variable In, Reference In) supplied thereto and producing first and second detector output signals (Q1, Q2) representative of said time and phase difference, offset correction means, delay means (D1, D2), said offset correction means being connected to receive said detector output signals (Q1, Q2) directly from said phase detector means and further connected to receive said detector output signals via said delay means (Q1A, Q2A) to produce offset correction signals (Q3, Q4), circuit means connected to receive said detector output signals from said phase detector means and said offset correction signals from said offset correction means and operative to supply control signals to an amplifier means thereby to control the operation of said amplifier means as a function of said detector output signals received from said phase detector means, and, amplifier means (113) responsive to said control signals supplied by said circuit means for producing an output signal.

Claim 14

A phase detector circuit with an automatic offset null, comprising, phase detector means for detecting the time and phase difference between a pair of input signals (Variable In, Reference In) supplied thereto and producing first and second detector output signals (Q1, Q2) representative of said time and phase difference, offset correction means, delay means (D1, D2), said offset correction means being connected to receive said detector output signals (Q1, Q2) directly from said phase detector means and further connected to receive said detector output signals via said delay means (Q1A, Q2A) to produce offset correction signals (Q3, Q4), circuit means connected to receive said detector output signals from said phase detector means and said offset correction signals from said offset correction means and operative to supply control signals to an amplifier means thereby to control the operation of said amplifier means as a function of said detector output signals received from said phase detector means, and, amplifier means (113) responsive to said control signals supplied by said circuit means for producing an output signal.

Claim 15

The circuit recited in claim 12 wherein, said delay means includes a first delay circuit responsive to one of said detector output signals for applying said one detector output signal to said offset correction means, and a second delay circuit responsive to the other detector output signal signal from said phase detector means for applying said other detector output signal to said offset correction means.

Claim 16

The circuit recited in claim 12 including, filter means connected between said offset correction means and said amplifier means.

Claim 17

The circuit recited in claim 12 wherein, said phase detector means comprises first and second flip flop means which receive a variable input signal and a reference input signal, respectively, and produce said first and second detector output signals, and said offset correction means comprises third and fourth flip flops means which directly receive said second and first detector output signals, respectively, and which receive said first and second detector output signals respectively, via said delay means, and produce first and second offset correction signals, respectively.