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US4598266A
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Modulo adder
Assignee: AG Communication Systems Corp
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Filing: 1984-09-24
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Granted: 1986-07-01
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Expires: 2004-09-24
Abstract
Abstract A modulo 2 2n -1 adder employing adders which may all be standard binary adders. A first binary adder sums binary input signals a and b to produce a first sum signal in which the n+2 more significant bits represent the integer part of (a+b)/2 2n (i.e., of a+b taken modulo 2 2n ). A second binary adder subtracts these n+2 more significant bits from a 2n bit shifted (less significant bits) version thereof for producing a first difference signal which is subtracted from the first sum signal in a third binary adder to produce a binary signal R. The signal R is applied to one input of a fourth binary adder which produces the desired modulo 2 2n -1 signal. A comparator circuit applies a constant (2 2n -1) to a difference input of the fourth binary adder only when R is greater than or equal to this constant.
Inventors
- 👤 Peter S. Bernardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:41
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/72; G06F7/729
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
Apparatus for converting binary signals a and b, which are made up of pluralities of binary bits, to a binary representation of the modulo p1*p3 sum thereof, said apparatus comprising: first means operative for summing the signals a and b for producing a first binary signal; second means responsive to bits of the first signal for producing a second binary signal which is proportional to the product of the constant 2 2n and the integer part of the first signal divided by 2 2n ; third means responsive to the second signal and said bits of the first signal for producing a third binary signal which is proportional to the difference between the second signal and the integer part of the first signal divided by 2 2n ; fourth means responsive to the first signal and the third signal for producing a fourth binary signal which is proportional to the difference therebetween; fifth means for generating a fifth binary signal that is proportional to a constant (2 2n -1); sixth means responsive to the fourth and fifth signals for passing the fifth signal as an output signal thereof only when said fourth signal is greater than or equal to said fifth binary signal representation of said constant (2 2n -1); and seventh means responsive to the fourth signal and the output signal of said sixth means for producing a seventh binary signal which is proportional to the difference therebetween and which corresponds to the desired output signal a+b taken modulo (2 2n -1).
Claim 2
Dependent Claim
253 words
Apparatus for converting binary signals a and b, which are made up of pluralities of binary bits, to a binary representation of the modulo p1*p3 sum thereof, said apparatus comprising: first means operative for summing the signals a and b for producing a first binary signal; second means responsive to bits of the first signal for producing a second binary signal which is proportional to the product of the constant 2 2n and the integer part of the first signal divided by 2 2n ; third means responsive to the second signal and said bits of the first signal for producing a third binary signal which is proportional to the difference between the second signal and the integer part of the first signal divided by 2 2n ; fourth means responsive to the first signal and the third signal for producing a fourth binary signal which is proportional to the difference therebetween; fifth means for generating a fifth binary signal that is proportional to a constant (2 2n -1); sixth means responsive to the fourth and fifth signals for passing the fifth signal as an output signal thereof only when said fourth signal is greater than or equal to said fifth binary signal representation of said constant (2 2n -1); and seventh means responsive to the fourth signal and the output signal of said sixth means for producing a seventh binary signal which is proportional to the difference therebetween and which corresponds to the desired output signal a+b taken modulo (2 2n -1).
Claim 3
Dependent Claim
14 words
Apparatus according to claim 1 wherein said first means comprises a first binary adder.
Claim 4
Dependent Claim
14 words
Apparatus according to claim 2 wherein said third means comprises a second binary adder.
Claim 5
Dependent Claim
53 words
Apparatus according to claim 3 further comprising eighth means coupling a prescribed number of the more significant bits of the first signal, which coupled bits correspond to the integer part of the first signal divided by 2 2n , as an eighth signal to a difference input terminal of said second binary adder.
Claim 6
Dependent Claim
61 words
Apparatus according to claim 4 wherein said second means inserts 2n binary 0's as less significant bits ahead of said prescribed number of more significant bits in the eighth signal to produce the second signal which is a bit shifted signal that corresponds to a product signal and which is applied to a sum input terminal of said second binary adder.
Claim 7
Dependent Claim
14 words
Apparatus according to claim 5 wherein said seventh means comprises a third binary adder.
Claim 8
Dependent Claim
78 words
Apparatus according to claim 6 wherein said sixth means comprises: comparator means operative for producing a binary output signal of other and one values when the fourth signal is less than and is greater than or equal to said constant (2 2n -1), respectively; and gate means responsive to other and one values of the sixth output signal of said comparator means for blocking and passing, respectively, the fifth binary signal representation of said constant (2 2n -1).
Claim 9
Dependent Claim
13 words
Apparatus according to claim 7 wherein said gate means comprises an AND-gate circuit.
Claim 10
Dependent Claim
15 words
Apparatus according to claim 7 wherein a and b comprise 3n+1 and 2n binary bits.
Claim 11
Dependent Claim
21 words
Apparatus according to claim 7 wherein said comparator means comprises a plurality of comparator circuits and a plurality of gate means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |