US4597805A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Making guard ring for reducing pattern sensitivity in MOS/LSI dynamic RAM
Assignee: Texas Instruments Inc
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Filing: 1985-02-15
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Granted: 1986-07-01
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Expires: 2005-02-15
Abstract
Abstract An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:10
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10B; H10B12/00; H10B12/30; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
109 words
A method of making a guard-ring in a face of a body of semiconductor material, the guard ring substantially surrounding an array of transistors at said face to prevent unwanted carriers from entering the area of said array, comprising the steps of: forming a deep heavily-doped region of one conductivity type in said body of semiconductor material adjacent said face thereof; the semiconductor material contiguous to said deep heavily-doped region being much more lightly doped with impurity of said one type, and thereafter forming a shallow heavily-doped region of opposite conductivity type above said deep heavily-doped region to provide guard ring surrounding a cell array area of said face.
Claim 2
Independent Claim
109 words
A method of making a guard-ring in a face of a body of semiconductor material, the guard ring substantially surrounding an array of transistors at said face to prevent unwanted carriers from entering the area of said array, comprising the steps of: forming a deep heavily-doped region of one conductivity type in said body of semiconductor material adjacent said face thereof; the semiconductor material contiguous to said deep heavily-doped region being much more lightly doped with impurity of said one type, and thereafter forming a shallow heavily-doped region of opposite conductivity type above said deep heavily-doped region to provide guard ring surrounding a cell array area of said face.
Claim 3
Dependent Claim
22 words
A method according to claim 1 wherein the body is P-, the deep region is P+, and the shallow region is N+.
Claim 4
Dependent Claim
32 words
A method according to claim 1 wherein the deep region is formed by implanting at high energy level to cause implant damage and locally lower the minority carrier lifetime in the body.
Claim 5
Dependent Claim
34 words
A method according to claim 2 including the steps of forming memory cells in said face on one side of the deep region and forming other circuitry in said face on the other side.
Claim 6
Dependent Claim
20 words
A method according to claim 4 wherein the deep region is formed in a ring completely surrounding said memory cells.
Claim 7
Dependent Claim
17 words
A method according to claim 4 wherein the memory cells include N-channel silicon-gate transistors and MOS capacitors.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |